vhaudiquet/u-boot-krane
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

rockchip: rk3588: Sync device tree with linux v6.7

Browse Source 
Sync rk3588 device tree from linux v6.7.

Also drop the rockchip,rk3568-dwc3 compatible now that dwc3-generic
driver support the rockchip,rk3588-dwc3 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
This commit is contained in:
Jonas Karlman
2024-02-04 18:47:25 +08:00
committed by Kever Yang
parent 473e54e795
commit 7c3e42b613
7 changed files with 47 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/dts/rk3588-turing-rk1.dtsi
+2 -2
View File
@@ -235,13 +235,13 @@
&pinctrl {
fan {
fan_int: fan-int {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
arch/arm/dts/rk3588-u-boot.dtsi
+1 -1
View File
@@ -7,7 +7,7 @@
/ {
usb_host1_xhci: usb@fc400000 {
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
arch/arm/dts/rk3588s-orangepi-5.dts
+1 -1
View File
@@ -38,7 +38,7 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 =<&leds_gpio>;
pinctrl-0 = <&leds_gpio>;
led-1 {
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
arch/arm/dts/rk3588s-pinctrl.dtsi
+1 -1
View File
@@ -369,7 +369,7 @@
emmc_data_strobe: emmc-data-strobe {
rockchip,pins =
/* emmc_data_strobe */
<2 RK_PA2 1 &pcfg_pull_none>;
<2 RK_PA2 1 &pcfg_pull_down>;
};
};
arch/arm/dts/rk3588s-u-boot.dtsi
+5 -28
View File
@@ -22,7 +22,7 @@
};
usb_host0_xhci: usb@fc000000 {
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfc000000 0x0 0x400000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
@@ -43,33 +43,6 @@
status = "disabled";
};
usb_host2_xhci: usb@fcd00000 {
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
reg = <0x0 0xfcd00000 0x0 0x400000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
<&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
<&cru CLK_PIPEPHY2_PIPE_U3_G>;
clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
dr_mode = "host";
phys = <&combphy2_psu PHY_TYPE_USB3>;
phy-names = "usb3-phy";
phy_type = "utmi_wide";
resets = <&cru SRST_A_USB3OTG2>;
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
status = "disabled";
};
pmu1_grf: syscon@fd58a000 {
bootph-all;
compatible = "rockchip,rk3588-pmu1-grf", "syscon";
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
usbdpphy0_grf: syscon@fd5c8000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5c8000 0x0 0x4000>;
@@ -206,6 +179,10 @@
status = "okay";
};
&pmu1grf {
bootph-all;
};
&scmi {
bootph-pre-ram;
};
arch/arm/dts/rk3588s.dtsi
+36
View File
@@ -443,6 +443,32 @@
status = "disabled";
};
usb_host2_xhci: usb@fcd00000 {
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
reg = <0x0 0xfcd00000 0x0 0x400000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
<&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
<&cru CLK_PIPEPHY2_PIPE_U3_G>;
clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
dr_mode = "host";
phys = <&combphy2_psu PHY_TYPE_USB3>;
phy-names = "usb3-phy";
phy_type = "utmi_wide";
resets = <&cru SRST_A_USB3OTG2>;
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
status = "disabled";
};
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x10000>;
};
sys_grf: syscon@fd58c000 {
compatible = "rockchip,rk3588-sys-grf", "syscon";
reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -1329,6 +1355,16 @@
};
};
dfi: dfi@fe060000 {
reg = <0x00 0xfe060000 0x00 0x10000>;
compatible = "rockchip,rk3588-dfi";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
rockchip,pmu = <&pmu1grf>;
};
gmac1: ethernet@fe1c0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1c0000 0x0 0x10000>;
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
+1 -1
View File
@@ -10,7 +10,7 @@
static const struct udevice_id rk3588_syscon_ids[] = {
{ .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
{ .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3588-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF },
{ .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF },
{ .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },