imx9: clock: Update clock init function and sequence

Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

arch/arm/include/asm/arch-imx9/clock.h

@@ -211,7 +211,8 @@ struct imx_clk_setting {
 	u32 div;
 };
 
-int clock_init(void);
+int clock_init_early(void);
+int clock_init_late(void);
 u32 get_clk_src_rate(enum ccm_clk_src source);
 u32 get_lpuart_clk(void);
 void init_uart_clk(u32 index);

arch/arm/mach-imx/imx9/clock.c

@@ -782,17 +782,10 @@ void bus_clock_init(void)
 	}
 }
 
-int clock_init(void)
+int clock_init_early(void)
 {
 	int i;
 
-	if (is_voltage_mode(VOLT_LOW_DRIVE)) {
-		bus_clock_init_low_drive();
-		set_arm_clk(MHZ(900));
-	} else {
-		bus_clock_init();
-	}
-
 	/* allow for non-secure access */
 	for (i = 0; i < OSCPLL_END; i++)
 		ccm_clk_src_tz_access(i, true, false, false);
@@ -809,6 +802,19 @@ int clock_init(void)
 	return 0;
 }
 
+/* Set bus and A55 core clock per voltage mode */
+int clock_init_late(void)
+{
+	if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+		bus_clock_init_low_drive();
+		set_arm_core_max_clk();
+	} else {
+		bus_clock_init();
+	}
+
+	return 0;
+}
+
 int set_clk_eqos(enum enet_freq type)
 {
 	u32 eqos_post_div;

arch/arm/mach-imx/imx9/soc.c

@@ -741,7 +741,7 @@ int arch_cpu_init(void)
 		/* Disable wdog */
 		init_wdog();
 
-		clock_init();
+		clock_init_early();
 
 		trdc_early_init();
 

board/freescale/imx93_evk/spl.c

@@ -123,9 +123,11 @@ void board_init_f(ulong dummy)
 		debug("LC: 0x%x\n", gd->arch.lifecycle);
 	}
 
+	clock_init_late();
+
 	power_init_board();
 
-	if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+	if (!is_voltage_mode(VOLT_LOW_DRIVE))
 		set_arm_clk(get_cpu_speed_grade_hz());
 
 	/* Init power of mix */

board/phytec/phycore_imx93/spl.c

@@ -130,7 +130,7 @@ void board_init_f(ulong dummy)
 		debug("LC: 0x%x\n", gd->arch.lifecycle);
 	}
 
-	clock_init();
+	clock_init_late();
 
 	power_init_board();