Merge tag 'fsl-qoriq-for-2026.10-rc3' of https://git.u-boot-project.org/u-boot/custodians/u-boot-fsl-qoriq

CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/946

- Add support for vendor protocol IDs 0x81 for SCMI
- Fix LDO selector boundaries and make the driver fail gracefully when
  the
- regulators DT node is absent for TPS65219 PMIC/Regulator:
- Fix a hotplug issue with pci_iommu_extra on Layerscape platforms for
  PCIe Layerscape.
- Fix a GIC LPI table corruption on LS1028A boards with 2 GiB of RAM
  caused by an unbounded TF-A DRAM bank loop and an integer underflow
  when gd->arch.resv_ram is inadvertently left at zero due to empty DRAM
  banks.
- Also includes a minor DT cosmetic cleanup.

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1402,32 +1402,43 @@ static int tfa_dram_init_banksize(void)
 		dram_size -= gd->dram[i].size;
 
 		i++;
-	} while (dram_size);
+	} while (dram_size && i < CONFIG_NR_DRAM_BANKS);
+
+	if (dram_size)
+		printf("Warning: CONFIG_NR_DRAM_BANKS is too small, %llx bytes left unassigned\n",
+		       dram_size);
 
 	if (i > 0)
 		ret = 0;
 
 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
 	/* Assign memory for MC */
-#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+#if defined(CONFIG_SYS_DDR_BLOCK3_BASE) && (CONFIG_NR_DRAM_BANKS >= 3)
-	if (gd->dram[2].size >=
+	if (gd->dram[2].size &&
+	    gd->dram[2].size >=
 	    board_reserve_ram_top(gd->dram[2].size)) {
 		gd->arch.resv_ram = gd->dram[2].start +
-			    gd->dram[2].size -
+			gd->dram[2].size -
-			    board_reserve_ram_top(gd->dram[2].size);
+			board_reserve_ram_top(gd->dram[2].size);
 	} else
 #endif
 	{
-		if (gd->dram[1].size >=
+#if defined(CFG_SYS_DDR_BLOCK2_BASE) && (CONFIG_NR_DRAM_BANKS >= 2)
+		if (gd->dram[1].size &&
+		    gd->dram[1].size >=
 		    board_reserve_ram_top(gd->dram[1].size)) {
 			gd->arch.resv_ram = gd->dram[1].start +
 				gd->dram[1].size -
 				board_reserve_ram_top(gd->dram[1].size);
-		} else if (gd->dram[0].size >
+		} else
-			   board_reserve_ram_top(gd->dram[0].size)) {
+#endif
-			gd->arch.resv_ram = gd->dram[0].start +
+		{
-				gd->dram[0].size -
+			if (gd->dram[0].size >
-				board_reserve_ram_top(gd->dram[0].size);
+			    board_reserve_ram_top(gd->dram[0].size)) {
+				gd->arch.resv_ram = gd->dram[0].start +
+					gd->dram[0].size -
+					board_reserve_ram_top(gd->dram[0].size);
+			}
 		}
 	}
 #endif	/* CONFIG_RESV_RAM */

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -65,6 +65,11 @@ int ls_gic_rd_tables_init(void *blob)
 	u64 gic_lpi_base;
 	int ret;
 
+	if (!gd->arch.resv_ram) {
+		debug("%s: failed to reserve memory for gic-lpi-tables\n", __func__);
+		return -ENOMEM;
+	}
+
 	gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
 	ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
 	if (ret)

arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi

@@ -25,28 +25,28 @@
 	status = "okay";
 	managed = "in-band-status";
 	phy-mode = "qsgmii";
-	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
+	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@8}>;
 };
 
 &mscc_felix_port1 {
 	status = "okay";
 	managed = "in-band-status";
 	phy-mode = "qsgmii";
-	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
+	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@9}>;
 };
 
 &mscc_felix_port2 {
 	status = "okay";
 	managed = "in-band-status";
 	phy-mode = "qsgmii";
-	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
+	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@a}>;
 };
 
 &mscc_felix_port3 {
 	status = "okay";
 	managed = "in-band-status";
 	phy-mode = "qsgmii";
-	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
+	phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@b}>;
 };
 
 &mscc_felix_port4 {

arch/arm/dts/fsl-ls1028a-qds.dtsi

@@ -147,7 +147,7 @@
 			mdio-parent-bus = <&enetc_mdio_pf3>;
 
 			/* on-board MDIO with a single RGMII PHY */
-			mdio@00 {
+			mdio@0 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <0x00>;

arch/arm/dts/fsl-ls1088a-qds.dtsi

@@ -41,7 +41,7 @@
 			mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
 			mdio-parent-bus = <&emdio1>;
 
-			mdio@00 {
+			mdio@0 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <0x00>;

arch/arm/dts/fsl-lx2160a-qds.dtsi

@@ -161,7 +161,7 @@
 			mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
 			mdio-parent-bus = <&emdio1>;
 
-			mdio@00 {
+			mdio@0 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <0x00>;
@@ -170,7 +170,7 @@
 					reg = <0x1>;
 				};
 			};
-			mdio@08 {
+			mdio@8 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <0x40>;

arch/arm/dts/fsl-sch-28021.dtsi

@@ -12,18 +12,18 @@
  * PHY addresses are 0x08 - 0x0b.
  * On the card the first port is the top port (farthest from PEX connector).
  */
-phy@08 {
+phy@8 {
 	reg = <0x08>;
 };
 
-phy@09 {
+phy@9 {
 	reg = <0x09>;
 };
 
-phy@0a {
+phy@a {
 	reg = <0x0a>;
 };
 
-phy@0b {
+phy@b {
 	reg = <0x0b>;
 };

cmd/scmi.c

@@ -30,6 +30,9 @@ struct {
 	{SCMI_PROTOCOL_ID_RESET_DOMAIN, "Reset domain management"},
 	{SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, "Voltage domain management"},
 	{SCMI_PROTOCOL_ID_PINCTRL, "Pin control management"},
+	{SCMI_PROTOCOL_ID_VENDOR_80, "Vendor specific (0x80)"},
+	{SCMI_PROTOCOL_ID_VENDOR_81, "Vendor specific (0x81)"},
+	{SCMI_PROTOCOL_ID_VENDOR_82, "Vendor specific (0x82)"},
 };
 
 /**

drivers/firmware/scmi/Kconfig

@@ -46,6 +46,9 @@ config SCMI_AGENT_OPTEE
 config SCMI_ID_VENDOR_80
 	bool
 
+config SCMI_ID_VENDOR_81
+	bool
+
 config SCMI_ID_VENDOR_82
 	bool
 

drivers/firmware/scmi/scmi_agent-uclass.c

@@ -116,6 +116,11 @@ struct udevice *scmi_get_protocol(struct udevice *dev,
 		proto = priv->vendor_dev_80;
 		break;
 #endif
+#if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_81)
+	case SCMI_PROTOCOL_ID_VENDOR_81:
+		proto = priv->vendor_dev_81;
+		break;
+#endif
 #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_82)
 	case SCMI_PROTOCOL_ID_VENDOR_82:
 		proto = priv->vendor_dev_82;
@@ -189,6 +194,11 @@ static int scmi_add_protocol(struct udevice *dev,
 		priv->vendor_dev_80 = proto;
 		break;
 #endif
+#if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_81)
+	case SCMI_PROTOCOL_ID_VENDOR_81:
+		priv->vendor_dev_81 = proto;
+		break;
+#endif
 #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_82)
 	case SCMI_PROTOCOL_ID_VENDOR_82:
 		priv->vendor_dev_82 = proto;

drivers/pci/pcie_layerscape_fixup.c

@@ -319,6 +319,11 @@ static struct extra_iommu_entry *get_extra_iommu_ents(void *blob,
 			/* Hot-plug entry */
 			entries[i].action = EXTRA_IOMMU_ENTRY_HOTPLUG;
 			p += 2;
+			/* Skip the comma separator so it check the
+			 * next "pci@" group.
+			 */
+			if (*p == ',')
+				p++;
 		} else if (!strncmp(p, "vfs", 3) ||
 			   !strncmp(p, "noari_vfs", 9)) {
 			/* VFs or VFs with ARI disabled entry */

drivers/power/pmic/tps65219.c

@@ -55,6 +55,7 @@ static int tps65219_bind(struct udevice *dev)
 	if (!ofnode_valid(regulators_node)) {
 		debug("%s: %s regulators subnode not found!\n", __func__,
 		      dev->name);
+		return -ENXIO;
 	}
 
 	debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);

include/power/tps65219.h

@@ -47,10 +47,10 @@
 #define TPS65219_LDO12_VOLT_MIN		 600000
 #define TPS65219_LDO12_VOLT_MAX		3400000
 #define TPS65219_LDO12_VOLT_REG_MIN	0
-#define TPS65219_LDO12_VOLT_REG_MAX	0x56
+#define TPS65219_LDO12_VOLT_REG_MAX	0x38
 #define TPS65219_LDO34_VOLT_MIN		1200000
 #define TPS65219_LDO34_VOLT_MAX		3300000
-#define TPS65219_LDO34_VOLT_REG_MIN	0x12
+#define TPS65219_LDO34_VOLT_REG_MIN	0x0c
-#define TPS65219_LDO34_VOLT_REG_MAX	0x54
+#define TPS65219_LDO34_VOLT_REG_MAX	0x36
 
 #endif /* TPS65219_H */

include/scmi_agent-uclass.h

@@ -58,6 +58,9 @@ struct scmi_agent_priv {
 #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_80)
 	struct udevice *vendor_dev_80;
 #endif
+#if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_81)
+	struct udevice *vendor_dev_81;
+#endif
 #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_82)
 	struct udevice *vendor_dev_82;
 #endif

include/scmi_protocols.h

@@ -26,6 +26,7 @@ enum scmi_std_protocol {
 	SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17,
 	SCMI_PROTOCOL_ID_PINCTRL = 0x19,
 	SCMI_PROTOCOL_ID_VENDOR_80 = 0x80,
+	SCMI_PROTOCOL_ID_VENDOR_81 = 0x81,
 	SCMI_PROTOCOL_ID_VENDOR_82 = 0x82,
 };
 
@@ -1340,7 +1341,7 @@ struct scmi_pinctrl_release_out {
 
 /* SCMI Pinctrl Config Types */
 enum scmi_config_type {
-	SCMI_PIN_DEFUALT = 0,
+	SCMI_PIN_DEFAULT = 0,
 	SCMI_PIN_BIAS_BUS_HOLD = 1,
 	SCMI_PIN_BIAS_DISABLE = 2,
 	SCMI_PIN_BIAS_HIGH_IMPEDANCE = 3,