From ce220f7f6407c3c6e3cae469cf7d80ad3cba20d9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 Jul 2026 14:02:47 +0200 Subject: [PATCH 1/8] cmd: scmi: Show names for vendor protocols 0x80 and 0x82 The generic SCMI vendor protocol IDs (0x80, 0x82) were listed by "scmi info" as . Add human readable names so the vendor protocols are easier to identify. Signed-off-by: Michal Simek Signed-off-by: Peng Fan --- cmd/scmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmd/scmi.c b/cmd/scmi.c index d0498b816aa..af974314583 100644 --- a/cmd/scmi.c +++ b/cmd/scmi.c @@ -30,6 +30,8 @@ struct { {SCMI_PROTOCOL_ID_RESET_DOMAIN, "Reset domain management"}, {SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, "Voltage domain management"}, {SCMI_PROTOCOL_ID_PINCTRL, "Pin control management"}, + {SCMI_PROTOCOL_ID_VENDOR_80, "Vendor specific (0x80)"}, + {SCMI_PROTOCOL_ID_VENDOR_82, "Vendor specific (0x82)"}, }; /** From fc55d1e91094666fd04c8351ad13dac3b0b2ddf9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 Jul 2026 14:02:48 +0200 Subject: [PATCH 2/8] firmware: scmi: Support probe vendor ID 0x81 Preparing to add the AMD/Xilinx SCMI vendor protocol driver, support probe of SCMI vendor ID 0x81. Add the protocol ID, the per-agent protocol device slot, the probe/lookup switch cases and the scmi command name, gated by a Kconfig option for conditional compilation. The same wiring has been done by commit 7830ccc77a13 ("firmware: scmi: Support probe vendor ID 0x80 and 0x82"). Signed-off-by: Michal Simek Signed-off-by: Peng Fan --- cmd/scmi.c | 1 + drivers/firmware/scmi/Kconfig | 3 +++ drivers/firmware/scmi/scmi_agent-uclass.c | 10 ++++++++++ include/scmi_agent-uclass.h | 3 +++ include/scmi_protocols.h | 1 + 5 files changed, 18 insertions(+) diff --git a/cmd/scmi.c b/cmd/scmi.c index af974314583..1aa20c7bd96 100644 --- a/cmd/scmi.c +++ b/cmd/scmi.c @@ -31,6 +31,7 @@ struct { {SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, "Voltage domain management"}, {SCMI_PROTOCOL_ID_PINCTRL, "Pin control management"}, {SCMI_PROTOCOL_ID_VENDOR_80, "Vendor specific (0x80)"}, + {SCMI_PROTOCOL_ID_VENDOR_81, "Vendor specific (0x81)"}, {SCMI_PROTOCOL_ID_VENDOR_82, "Vendor specific (0x82)"}, }; diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig index cd912ebe409..64bc9aef5af 100644 --- a/drivers/firmware/scmi/Kconfig +++ b/drivers/firmware/scmi/Kconfig @@ -46,6 +46,9 @@ config SCMI_AGENT_OPTEE config SCMI_ID_VENDOR_80 bool +config SCMI_ID_VENDOR_81 + bool + config SCMI_ID_VENDOR_82 bool diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index cd458a7f458..9159e59385b 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -116,6 +116,11 @@ struct udevice *scmi_get_protocol(struct udevice *dev, proto = priv->vendor_dev_80; break; #endif +#if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_81) + case SCMI_PROTOCOL_ID_VENDOR_81: + proto = priv->vendor_dev_81; + break; +#endif #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_82) case SCMI_PROTOCOL_ID_VENDOR_82: proto = priv->vendor_dev_82; @@ -189,6 +194,11 @@ static int scmi_add_protocol(struct udevice *dev, priv->vendor_dev_80 = proto; break; #endif +#if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_81) + case SCMI_PROTOCOL_ID_VENDOR_81: + priv->vendor_dev_81 = proto; + break; +#endif #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_82) case SCMI_PROTOCOL_ID_VENDOR_82: priv->vendor_dev_82 = proto; diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index c40b448bcba..c9d77ad8ec7 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -58,6 +58,9 @@ struct scmi_agent_priv { #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_80) struct udevice *vendor_dev_80; #endif +#if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_81) + struct udevice *vendor_dev_81; +#endif #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_82) struct udevice *vendor_dev_82; #endif diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index a8fd0a5a729..801912d16a9 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -26,6 +26,7 @@ enum scmi_std_protocol { SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17, SCMI_PROTOCOL_ID_PINCTRL = 0x19, SCMI_PROTOCOL_ID_VENDOR_80 = 0x80, + SCMI_PROTOCOL_ID_VENDOR_81 = 0x81, SCMI_PROTOCOL_ID_VENDOR_82 = 0x82, }; From 607d45d1e3b3f0e2b2a2e23799e8b43cd52a28da Mon Sep 17 00:00:00 2001 From: Kumara Bhimeswararao Matsa Date: Wed, 29 Jul 2026 16:42:18 +0530 Subject: [PATCH 3/8] power: pmic: tps65219: fail if regulators node is missing The TPS65219 bind function continues when the regulators subnode is missing. This causes pmic_bind_children() to be called with an invalid ofnode and permits a misleading message indicating that the subnode was found. Return -ENXIO when the regulators subnode is absent, matching the behavior of other TI PMIC drivers. Signed-off-by: Kumara Bhimeswararao Matsa Signed-off-by: Peng Fan --- drivers/power/pmic/tps65219.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/pmic/tps65219.c b/drivers/power/pmic/tps65219.c index 0716af027a3..1fecde84795 100644 --- a/drivers/power/pmic/tps65219.c +++ b/drivers/power/pmic/tps65219.c @@ -55,6 +55,7 @@ static int tps65219_bind(struct udevice *dev) if (!ofnode_valid(regulators_node)) { debug("%s: %s regulators subnode not found!\n", __func__, dev->name); + return -ENXIO; } debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); From d13ee7acafb93a8b8753083ee82a594da121f745 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Thu, 30 Jul 2026 00:07:36 +0200 Subject: [PATCH 4/8] arm: dts: layerscape: drop leading zeros from unit addresses Fix many dtc warning for the Layerscape device trees with W=1. Without this fix, it emits over 30 unit_address_format warnings. No functional change. Signed-off-by: Vincent Jardin Signed-off-by: Peng Fan --- arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 8 ++++---- arch/arm/dts/fsl-ls1028a-qds.dtsi | 2 +- arch/arm/dts/fsl-ls1088a-qds.dtsi | 2 +- arch/arm/dts/fsl-lx2160a-qds.dtsi | 4 ++-- arch/arm/dts/fsl-sch-28021.dtsi | 8 ++++---- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index b6522069207..529adfcbaf4 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -25,28 +25,28 @@ status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@8}>; }; &mscc_felix_port1 { status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@9}>; }; &mscc_felix_port2 { status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@a}>; }; &mscc_felix_port3 { status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@b}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index ac5b2d9dde9..92757260560 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -147,7 +147,7 @@ mdio-parent-bus = <&enetc_mdio_pf3>; /* on-board MDIO with a single RGMII PHY */ - mdio@00 { + mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0x00>; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi index 83635a2e40d..5bdc8675aa2 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -41,7 +41,7 @@ mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5 mdio-parent-bus = <&emdio1>; - mdio@00 { + mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0x00>; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 6fa36de0622..c213088bdf0 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -161,7 +161,7 @@ mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 mdio-parent-bus = <&emdio1>; - mdio@00 { + mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0x00>; @@ -170,7 +170,7 @@ reg = <0x1>; }; }; - mdio@08 { + mdio@8 { #address-cells = <1>; #size-cells = <0>; reg = <0x40>; diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi index 61245287b96..d819308ed8c 100644 --- a/arch/arm/dts/fsl-sch-28021.dtsi +++ b/arch/arm/dts/fsl-sch-28021.dtsi @@ -12,18 +12,18 @@ * PHY addresses are 0x08 - 0x0b. * On the card the first port is the top port (farthest from PEX connector). */ -phy@08 { +phy@8 { reg = <0x08>; }; -phy@09 { +phy@9 { reg = <0x09>; }; -phy@0a { +phy@a { reg = <0x0a>; }; -phy@0b { +phy@b { reg = <0x0b>; }; From 289b1bae1c798b12729f5467fcb34fffa49ef9a8 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Thu, 30 Jul 2026 00:21:17 +0200 Subject: [PATCH 5/8] pci: layerscape: fix pci_iommu_extra hotplug We can have many pci hotplug groups, each introduced by a "pci@" token such as, pci_iommu_extra=pci@0x3600000,1.0.0,hp,pci@0x3700000,1.0.0,hp, pci@0x3800000,1.0.0,hp,pci@0x3900000,1.0.0,hp Without this fix, we have the error: Added iommu map for hotplug 1.0.0 ERROR: invalid action in extra iommu entry ERROR: invalid action in extra iommu entry ERROR: invalid action in extra iommu entry Fixes: 2a5bbb13cc39 ("pci: layerscape: add a way of specifying additional iommu mappings") Signed-off-by: Vincent Jardin Reviewed-by: Neil Armstrong Signed-off-by: Peng Fan --- drivers/pci/pcie_layerscape_fixup.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 97c38c0bfa7..5299aee63db 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -319,6 +319,11 @@ static struct extra_iommu_entry *get_extra_iommu_ents(void *blob, /* Hot-plug entry */ entries[i].action = EXTRA_IOMMU_ENTRY_HOTPLUG; p += 2; + /* Skip the comma separator so it check the + * next "pci@" group. + */ + if (*p == ',') + p++; } else if (!strncmp(p, "vfs", 3) || !strncmp(p, "noari_vfs", 9)) { /* VFs or VFs with ARI disabled entry */ From d57e3e4c75951a7e4b98d31bcde4a95b058b66e5 Mon Sep 17 00:00:00 2001 From: Kumara Bhimeswararao Matsa Date: Thu, 6 Aug 2026 06:28:03 +0530 Subject: [PATCH 6/8] power: regulator: tps65219: Fix LDO selector boundaries According to the TPS65219 datasheet, selectors 0x38 through 0x3f saturate at 3.4 V for LDO1 and LDO2. For LDO3 and LDO4, selectors 0x00 through 0x0c saturate at 1.2 V, while selectors 0x36 through 0x3f saturate at 3.3 V. The driver currently uses 0x56, 0x12, and 0x54 as selector boundary values. These values do not match the selector boundaries defined by the datasheet. Use the correct selector boundary values of 0x38, 0x0c, and 0x36 for interpolation. Fixes: b5cfa0c7ca4f ("power: add driver for the TPS65219 PMIC") Signed-off-by: Kumara Bhimeswararao Matsa Acked-by: Maarten Brock Signed-off-by: Peng Fan --- include/power/tps65219.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/power/tps65219.h b/include/power/tps65219.h index e8780af2d81..c3114f26e1d 100644 --- a/include/power/tps65219.h +++ b/include/power/tps65219.h @@ -47,10 +47,10 @@ #define TPS65219_LDO12_VOLT_MIN 600000 #define TPS65219_LDO12_VOLT_MAX 3400000 #define TPS65219_LDO12_VOLT_REG_MIN 0 -#define TPS65219_LDO12_VOLT_REG_MAX 0x56 +#define TPS65219_LDO12_VOLT_REG_MAX 0x38 #define TPS65219_LDO34_VOLT_MIN 1200000 #define TPS65219_LDO34_VOLT_MAX 3300000 -#define TPS65219_LDO34_VOLT_REG_MIN 0x12 -#define TPS65219_LDO34_VOLT_REG_MAX 0x54 +#define TPS65219_LDO34_VOLT_REG_MIN 0x0c +#define TPS65219_LDO34_VOLT_REG_MAX 0x36 #endif /* TPS65219_H */ From 9f82dcd489246c66eb780235d1fedb536771c787 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Mon, 10 Aug 2026 13:45:31 +0530 Subject: [PATCH 7/8] scmi: pinctrl: Rename SCMI_PIN_DEFUALT to SCMI_PIN_DEFAULT Fix typo in enum scmi_config_type in include/scmi_protocols.h. The enum value SCMI_PIN_DEFUALT was misspelled and should be SCMI_PIN_DEFAULT to match the correct English spelling. This fixes potential compilation issues and improves code clarity for any code that references this enum value Fixes: 0cb160f1b629 ("scmi: pinctrl: add pinctrl driver for SCMI") Signed-off-by: Udit Kumar Signed-off-by: Peng Fan --- include/scmi_protocols.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 801912d16a9..86165f8ba5e 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -1341,7 +1341,7 @@ struct scmi_pinctrl_release_out { /* SCMI Pinctrl Config Types */ enum scmi_config_type { - SCMI_PIN_DEFUALT = 0, + SCMI_PIN_DEFAULT = 0, SCMI_PIN_BIAS_BUS_HOLD = 1, SCMI_PIN_BIAS_DISABLE = 2, SCMI_PIN_BIAS_HIGH_IMPEDANCE = 3, From 5a32ebc96295795a7325d6cbaa2d8b0bdfaa6d75 Mon Sep 17 00:00:00 2001 From: Patryk Biel Date: Tue, 14 Jul 2026 11:49:14 +0200 Subject: [PATCH 8/8] armv8: layerscape: Fix TF-A DRAM reservation with empty banks The TF-A DRAM bank setup currently assumes that the number of banks reported by TF-A matches the number of entries available in gd->bd->bi_dram[]. Limit the loop by CONFIG_NR_DRAM_BANKS so that a platform with fewer configured DRAM banks does not write past the array. The reserved RAM setup also checks higher DRAM banks before falling back to bank 0. When a higher bank is empty and board_reserve_ram_top() returns 0, the old test succeeds for a zero-sized bank. This can set gd->arch.resv_ram to 0. On systems with CONFIG_GIC_V3_ITS this value is later used by ls_gic_rd_tables_init() to place the GIC LPI tables: gd->arch.resv_ram - GIC_LPI_SIZE If gd->arch.resv_ram is 0, the subtraction underflows and the GIC LPI tables are placed at an invalid high address. Skip empty banks when selecting the reserved RAM area and fail GIC LPI table setup if no reserved RAM address was established. This fixes LS1028A systems with 2 GiB of RAM, where TF-A reports only one populated DRAM bank. Tested on an LS1028ARDB with TF-A modified to report 2 GiB of RAM, and on a custom LS1028A-based board equipped with 2 GiB of RAM. Signed-off-by: Patryk Biel Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 33 ++++++++++++++++--------- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 ++++ 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 88adcf35432..37687a96600 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1402,32 +1402,43 @@ static int tfa_dram_init_banksize(void) dram_size -= gd->dram[i].size; i++; - } while (dram_size); + } while (dram_size && i < CONFIG_NR_DRAM_BANKS); + + if (dram_size) + printf("Warning: CONFIG_NR_DRAM_BANKS is too small, %llx bytes left unassigned\n", + dram_size); if (i > 0) ret = 0; #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ -#ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->dram[2].size >= +#if defined(CONFIG_SYS_DDR_BLOCK3_BASE) && (CONFIG_NR_DRAM_BANKS >= 3) + if (gd->dram[2].size && + gd->dram[2].size >= board_reserve_ram_top(gd->dram[2].size)) { gd->arch.resv_ram = gd->dram[2].start + - gd->dram[2].size - - board_reserve_ram_top(gd->dram[2].size); + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->dram[1].size >= +#if defined(CFG_SYS_DDR_BLOCK2_BASE) && (CONFIG_NR_DRAM_BANKS >= 2) + if (gd->dram[1].size && + gd->dram[1].size >= board_reserve_ram_top(gd->dram[1].size)) { gd->arch.resv_ram = gd->dram[1].start + gd->dram[1].size - board_reserve_ram_top(gd->dram[1].size); - } else if (gd->dram[0].size > - board_reserve_ram_top(gd->dram[0].size)) { - gd->arch.resv_ram = gd->dram[0].start + - gd->dram[0].size - - board_reserve_ram_top(gd->dram[0].size); + } else +#endif + { + if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); + } } } #endif /* CONFIG_RESV_RAM */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d85a630f8a3..24ccb8bb0c4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -65,6 +65,11 @@ int ls_gic_rd_tables_init(void *blob) u64 gic_lpi_base; int ret; + if (!gd->arch.resv_ram) { + debug("%s: failed to reserve memory for gic-lpi-tables\n", __func__); + return -ENOMEM; + } + gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE); if (ret)