vhaudiquet/u-boot-krane
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: zynqmp: Move board_early_init_r clock setup to mach code

Browse Source 
board_early_init_r() programmed the system timestamp counter directly
with readl()/writel() in board code. This is SoC register setup rather
than board policy, and similar code exists across the Xilinx SoCs.

Move it into zynqmp_timer_setup() in arch/arm/mach-zynqmp so the board
hook only keeps the EL3 guard and calls the helper. The asm/arch/clk.h
include (for zynqmp_get_system_timer_freq()) moves to cpu.c along with
the code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/2d8f2419fab314b4ff8fd53b846e1dd6151586d3.1782219202.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
2026-07-08 08:55:51 +02:00
parent d885e802ce
commit 722cd61c35
3 changed files with 25 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/mach-zynqmp/cpu.c
+22
View File
@@ -8,6 +8,7 @@
#include <time.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/armv8/mmu.h>
@@ -234,6 +235,27 @@ int zynqmp_mmio_read(const u32 address, u32 *value)
return ret;
}
void zynqmp_timer_setup(void)
{
u32 val;
val = readl(&crlapb_base->timestamp_ref_ctrl);
val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
if (!val) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
/* Program freq register in System counter */
writel(zynqmp_get_system_timer_freq(),
&iou_scntr_secure->base_frequency_id_register);
/* And enable system counter */
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
&iou_scntr_secure->counter_control_register);
}
}
U_BOOT_DRVINFO(soc_xilinx_zynqmp) = {
.name = "soc_xilinx_zynqmp",
};
arch/arm/mach-zynqmp/include/mach/sys_proto.h
+2
View File
@@ -54,5 +54,7 @@ void mem_map_fill(void);
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
void tcm_init(enum tcm_mode mode);
#endif
/* EL3 clock/timer register setup, called from board_early_init_r() */
void zynqmp_timer_setup(void);
#endif /* _ASM_ARCH_SYS_PROTO_H */
board/xilinx/zynqmp/zynqmp.c
+1 -17
View File
@@ -24,7 +24,6 @@
#include <malloc.h>
#include <memalign.h>
#include <wdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/psu_init_gpl.h>
@@ -214,26 +213,11 @@ int board_init(void)
int board_early_init_r(void)
{
u32 val;
if (current_el() != 3)
return 0;
val = readl(&crlapb_base->timestamp_ref_ctrl);
val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
zynqmp_timer_setup();
if (!val) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
/* Program freq register in System counter */
writel(zynqmp_get_system_timer_freq(),
&iou_scntr_secure->base_frequency_id_register);
/* And enable system counter */
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
&iou_scntr_secure->counter_control_register);
}
return 0;
}