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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26455

Thanks Conor and Yao for catching this issue.

- Revert "RISC-V 32/64 images support" to fix compatibility issue
This commit is contained in:
Tom Rini
2025-06-02 08:40:37 -06:00
parent b22a276f03 31e215fde8
commit 6f657c64c9
6 changed files with 8 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/riscv/dts/binman.dtsi
+4 -10
View File
@@ -5,12 +5,6 @@
#include <config.h>
#ifdef CONFIG_64BIT
#define ARCH "riscv64"
#else
#define ARCH "riscv"
#endif
/ {
binman: binman {
multiple-images;
@@ -37,7 +31,7 @@
description = "U-Boot";
type = "standalone";
os = "U-Boot";
arch = ARCH;
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
@@ -49,7 +43,7 @@
description = "Linux";
type = "standalone";
os = "Linux";
arch = ARCH;
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
@@ -62,7 +56,7 @@
tee {
description = "OP-TEE";
type = "tee";
arch = ARCH;
arch = "riscv";
compression = "none";
os = "tee";
load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>;
@@ -76,7 +70,7 @@
description = "OpenSBI fw_dynamic Firmware";
type = "firmware";
os = "opensbi";
arch = ARCH;
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
arch/riscv/include/asm/u-boot.h
-4
View File
@@ -23,10 +23,6 @@
#include <asm/u-boot-riscv.h>
/* For image.h:image_check_target_arch() */
#ifdef CONFIG_64BIT
#define IH_ARCH_DEFAULT IH_ARCH_RISCV64
#else
#define IH_ARCH_DEFAULT IH_ARCH_RISCV
#endif
#endif /* _U_BOOT_H_ */
arch/riscv/lib/bootm.c
-4
View File
@@ -90,10 +90,6 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
announce_and_cleanup(fake);
if (!fake) {
if (images->os.arch != IH_ARCH_DEFAULT) {
printf("Image arch not compatible with host arch.\n");
hang();
}
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
#ifdef CONFIG_SMP
ret = smp_call_function(images->ep,
boot/image.c
+1 -2
View File
@@ -92,8 +92,7 @@ static const table_entry_t uimage_arch[] = {
{ IH_ARCH_ARC, "arc", "ARC", },
{ IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ IH_ARCH_XTENSA, "xtensa", "Xtensa", },
{ IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",},
{ IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",},
{ IH_ARCH_RISCV, "riscv", "RISC-V", },
{ -1, "", "", },
};
cmd/booti.c
+2 -5
View File
@@ -130,11 +130,8 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
if (IS_ENABLED(CONFIG_RISCV))
if (IS_ENABLED(CONFIG_64BIT))
images.os.arch = IH_ARCH_RISCV64;
else
images.os.arch = IH_ARCH_RISCV;
if (IS_ENABLED(CONFIG_RISCV_SMODE))
images.os.arch = IH_ARCH_RISCV;
else if (IS_ENABLED(CONFIG_ARM64))
images.os.arch = IH_ARCH_ARM64;
include/image.h
+1 -2
View File
@@ -138,8 +138,7 @@ enum {
IH_ARCH_ARC, /* Synopsys DesignWare ARC */
IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */
IH_ARCH_XTENSA, /* Xtensa */
IH_ARCH_RISCV, /* RISC-V 32 bit*/
IH_ARCH_RISCV64, /* RISC-V 64 bit*/
IH_ARCH_RISCV, /* RISC-V */
IH_ARCH_COUNT,
};