Merge tag 'u-boot-imx-master-20240415' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20348 - Update the imx_rgpio2p to only access one address as per the dt-schema. - Remove unused imx9_cpu.c file. - Only use the LPUART ipg clk for i.MX7ULP. - Use the correct anatop base for accessing the PLL clocks on i.MX93.
This commit is contained in:
Tom Rini
@@ -289,7 +289,7 @@ static int imx93_clk_probe(struct udevice *dev)
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clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2,
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imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
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base = (void *)ANATOP_BASE_ADDR;
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anatop_base = (void *)ANATOP_BASE_ADDR;
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clk_dm(IMX93_CLK_ARM_PLL,
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imx_clk_fracn_gppll_integer("arm_pll", "clock-osc-24m",
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@@ -1,224 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <thermal.h>
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#include <asm/global_data.h>
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#include <asm/system.h>
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#include <firmware/linux/imx/sci/sci.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-imx/cpu.h>
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#include <asm/armv8/cpu.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct cpu_imx_plat {
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const char *name;
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const char *rev;
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const char *type;
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u32 cpu_rsrc;
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u32 cpurev;
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u32 freq_mhz;
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u32 mpidr;
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};
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const char *get_imx9_type(u32 imxtype)
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{
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switch (imxtype) {
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case MXC_CPU_IMX93:
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return "93";
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default:
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return "??";
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}
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}
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const char *get_imx9_rev(u32 rev)
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{
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switch (rev) {
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case CHIP_REV_1_0:
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return "1.";
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case CHIP_REV_B:
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return "B";
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case CHIP_REV_C:
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return "C";
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default:
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return "?";
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}
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}
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static void set_core_data(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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if (device_is_compatible(dev, "arm,cortex-a35"))
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plat->name = "A35";
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else
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plat->name = "?";
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}
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#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
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static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
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{
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struct udevice *thermal_dev;
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int cpu_tmp, ret;
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int idx = 1; /* use "cpu-thermal0" device */
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if (plat->cpu_rsrc == SC_R_A72)
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idx = 2; /* use "cpu-thermal1" device */
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ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
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if (!ret) {
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ret = thermal_get_temp(thermal_dev, &cpu_tmp);
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if (ret)
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return 0xdeadbeef;
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} else {
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return 0xdeadbeef;
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}
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return cpu_tmp;
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}
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#else
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static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
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{
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return 0;
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}
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#endif
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int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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int ret, temp;
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if (size < 100)
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return -ENOSPC;
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ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
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plat->type, plat->rev, plat->name, plat->freq_mhz);
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if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
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temp = cpu_imx_get_temp(plat);
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buf = buf + ret;
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size = size - ret;
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if (temp != 0xdeadbeef)
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ret = snprintf(buf, size, " at %dC", temp);
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else
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ret = snprintf(buf, size, " - invalid sensor data");
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}
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snprintf(buf + ret, size - ret, "\n");
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return 0;
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}
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static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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info->cpu_freq = plat->freq_mhz * 1000;
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info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
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return 0;
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}
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static int cpu_imx_get_count(const struct udevice *dev)
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{
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ofnode node;
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int num = 0;
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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if (!ofnode_is_enabled(node))
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continue;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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if (!strcmp(device_type, "cpu"))
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num++;
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}
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return num;
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}
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static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size)
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{
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snprintf(buf, size, "NXP");
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return 0;
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}
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static int cpu_imx_is_current(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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if (plat->mpidr == (read_mpidr() & 0xffff))
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return 1;
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return 0;
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}
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static const struct cpu_ops cpu_imx9_ops = {
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.get_desc = cpu_imx_get_desc,
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.get_info = cpu_imx_get_info,
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.get_count = cpu_imx_get_count,
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.get_vendor = cpu_imx_get_vendor,
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.is_current = cpu_imx_is_current,
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};
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static const struct udevice_id cpu_imx9_ids[] = {
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{ .compatible = "arm,cortex-a35" },
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{ .compatible = "arm,cortex-a53" },
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{ .compatible = "arm,cortex-a72" },
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{ }
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};
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static ulong imx9_get_cpu_rate(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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ulong rate;
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int ret;
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ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
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(sc_pm_clock_rate_t *)&rate);
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if (ret) {
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printf("Could not read CPU frequency: %d\n", ret);
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return 0;
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}
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return rate;
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}
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static int imx9_cpu_probe(struct udevice *dev)
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{
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struct cpu_imx_plat *plat = dev_get_plat(dev);
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u32 cpurev;
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set_core_data(dev);
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cpurev = get_cpu_rev();
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plat->cpurev = cpurev;
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plat->rev = get_imx9_rev(cpurev & 0xFFF);
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plat->type = get_imx9_type((cpurev & 0xFF000) >> 12);
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plat->freq_mhz = imx9_get_cpu_rate(dev) / 1000000;
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plat->mpidr = dev_read_addr(dev);
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if (plat->mpidr == FDT_ADDR_T_NONE) {
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printf("%s: Failed to get CPU reg property\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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U_BOOT_DRIVER(cpu_imx9_drv) = {
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.name = "imx9x_cpu",
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.id = UCLASS_CPU,
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.of_match = cpu_imx9_ids,
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.ops = &cpu_imx9_ops,
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.probe = imx9_cpu_probe,
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.plat_auto = sizeof(struct cpu_imx_plat),
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.flags = DM_FLAG_PRE_RELOC,
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};
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@@ -21,6 +21,12 @@ enum imx_rgpio2p_direction {
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#define GPIO_PER_BANK 32
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struct imx_rgpio2p_soc_data {
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bool have_dual_base;
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};
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#define IMX8ULP_GPIO_BASE_OFF 0x40
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struct imx_rgpio2p_data {
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struct gpio_regs *regs;
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};
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@@ -165,6 +171,9 @@ static int imx_rgpio2p_probe(struct udevice *dev)
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static int imx_rgpio2p_bind(struct udevice *dev)
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{
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struct imx_rgpio2p_plat *plat = dev_get_plat(dev);
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struct imx_rgpio2p_soc_data *data =
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(struct imx_rgpio2p_soc_data *)dev_get_driver_data(dev);
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bool dual_base = data->have_dual_base;
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fdt_addr_t addr;
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/*
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@@ -176,9 +185,26 @@ static int imx_rgpio2p_bind(struct udevice *dev)
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if (plat)
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return 0;
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addr = devfdt_get_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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/*
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* Handle legacy compatible combinations which used two reg values
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* for the i.MX8ULP and i.MX93.
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*/
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if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
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(device_is_compatible(dev, "fsl,imx93-gpio") ||
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(device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
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dual_base = true;
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if (dual_base) {
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addr = devfdt_get_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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} else {
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addr = devfdt_get_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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addr += IMX8ULP_GPIO_BASE_OFF;
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}
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/*
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* TODO:
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@@ -202,9 +228,17 @@ static int imx_rgpio2p_bind(struct udevice *dev)
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return 0;
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}
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static struct imx_rgpio2p_soc_data imx7ulp_data = {
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.have_dual_base = true,
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};
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static struct imx_rgpio2p_soc_data imx8ulp_data = {
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.have_dual_base = false,
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};
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static const struct udevice_id imx_rgpio2p_ids[] = {
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{ .compatible = "fsl,imx7ulp-gpio" },
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{ .compatible = "fsl,imx7ulp-gpio", .data = (ulong)&imx7ulp_data },
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{ .compatible = "fsl,imx8ulp-gpio", .data = (ulong)&imx8ulp_data },
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{ }
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};
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@@ -109,28 +109,35 @@ u32 __weak get_lpuart_clk(void)
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}
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#if CONFIG_IS_ENABLED(CLK)
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static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
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static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk_rate)
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{
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struct clk per_clk;
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struct lpuart_serial_plat *plat = dev_get_plat(dev);
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struct clk clk;
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ulong rate;
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int ret;
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char *name;
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ret = clk_get_by_name(dev, "per", &per_clk);
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if (plat->devtype == DEV_MX7ULP)
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name = "ipg";
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else
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name = "per";
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ret = clk_get_by_name(dev, name, &clk);
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if (ret) {
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dev_err(dev, "Failed to get per clk: %d\n", ret);
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dev_err(dev, "Failed to get clk: %d\n", ret);
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return ret;
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}
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rate = clk_get_rate(&per_clk);
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rate = clk_get_rate(&clk);
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if ((long)rate <= 0) {
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dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
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dev_err(dev, "Failed to get clk rate: %ld\n", (long)rate);
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return ret;
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}
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*clk = rate;
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*clk_rate = rate;
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return 0;
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}
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#else
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static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
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static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk_rate)
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{ return -ENOSYS; }
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#endif
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@@ -479,19 +486,22 @@ static int lpuart_serial_pending(struct udevice *dev, bool input)
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static int lpuart_serial_probe(struct udevice *dev)
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{
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#if CONFIG_IS_ENABLED(CLK)
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struct lpuart_serial_plat *plat = dev_get_plat(dev);
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struct clk per_clk;
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struct clk ipg_clk;
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int ret;
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ret = clk_get_by_name(dev, "per", &per_clk);
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if (!ret) {
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ret = clk_enable(&per_clk);
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if (ret) {
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dev_err(dev, "Failed to enable per clk: %d\n", ret);
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return ret;
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if (plat->devtype != DEV_MX7ULP) {
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ret = clk_get_by_name(dev, "per", &per_clk);
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if (!ret) {
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ret = clk_enable(&per_clk);
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if (ret) {
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dev_err(dev, "Failed to enable per clk: %d\n", ret);
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return ret;
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}
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} else {
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debug("%s: Failed to get per clk: %d\n", __func__, ret);
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}
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} else {
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debug("%s: Failed to get per clk: %d\n", __func__, ret);
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}
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ret = clk_get_by_name(dev, "ipg", &ipg_clk);
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Block a user