vhaudiquet/u-boot-krane
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

stm32mp: Fix handling of OPTEE in the middle of DRAM

Browse Source 
STM32MP13xx may have OPTEE-OS at 0xdd000000 even on systems with 1 GiB
of DRAM at 0xc0000000, which is not the end of DRAM anymore. This puts
the OPTEE-OS in the middle of DRAM. Currently, the code sets RAM top to
0xdd000000 and prevents the DRAM range past OPTEE at 0xe0000000..0xffffffff
from being set as cacheable and from being usable. The code also sets the
area over OPTEE as invalid region in MMU tables, which is not correct.

Adjust the code such, that it only ever sets RAM top just before OPTEE
in case the OPTEE is really at the end of DRAM, mainly to be backward
compatible. Furthermore, adjust the MMU table configuration such, that
the regions over the OPTEE are simply skipped and not reconfigured, and
the regions between end of OPTEE and RAM top are set as cacheable, if
any actually exist.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Marek Vasut
2025-12-05 11:38:38 +01:00
committed by Patrice Chotard
parent 59f9fcc1f5
commit 6c78933df8
2 changed files with 9 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/mach-stm32mp/dram_init.c
+3 -1
View File
@@ -65,6 +65,7 @@ int dram_init(void)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_addr_t top = gd->ram_top;
phys_size_t size;
phys_addr_t reg;
u32 optee_start, optee_size;
@@ -86,7 +87,8 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
/* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */
if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) {
if (!optee_get_reserved_memory(&optee_start, &optee_size))
reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
if (optee_start + optee_size == top)
reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
}
/* before relocation, mark the U-Boot memory as cacheable by default */
arch/arm/mach-stm32mp/stm32mp1/cpu.c
+6 -5
View File
@@ -82,11 +82,12 @@ void dram_bank_mmu_setup(int bank)
i++) {
addr = i << MMU_SECTION_SHIFT;
option = DCACHE_DEFAULT_OPTION;
if (use_lmb &&
(lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) ||
(gd->ram_top && addr >= gd->ram_top))
)
option = 0; /* INVALID ENTRY in TLB */
if (use_lmb) {
if (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP))
continue;
if (gd->ram_top && addr >= gd->ram_top)
option = 0; /* INVALID ENTRY in TLB */
}
set_section_dcache(i, option);
}
}