Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
This is R-Car X5H support. It was originally posted before rc1 and the changes are well isolated. This is the final patchset which enables the Gen5 drivers that are already in tree. I waited with this a bit until the SCMI ID discussion stabilized and TFA X5H support landed. So now, I can add the final piece into U-Boot too. Note that this is still very much experimental, the X5H upstreaming is in very early stages. The OF_UPSTREAM conversion will happen likely in 2026.04 or 2026.07 window, depending on when the Linux DTs land. The compound-clock.c is surely going to go away once SCP gets updated and the MFIS mailbox will be reworked once upstream bindings get developed. This also includes SH DT alignment fix.
This commit is contained in:
Tom Rini
@@ -1499,6 +1499,15 @@ ifeq ($(CONFIG_POSITION_INDEPENDENT)$(CONFIG_RCAR_GEN3),yy)
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OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x50000000
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endif
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ifeq ($(CONFIG_POSITION_INDEPENDENT)$(CONFIG_RCAR_GEN5),yy)
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# The flash_writer tool and previous recovery tools
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# require the SREC load address to be 0x8e30_0000 .
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# The PIE U-Boot build sets the address to 0x0, so
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# override the address back to make u-boot-elf.srec
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# compatible with the recovery tools.
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OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x8e300000
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endif
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u-boot-elf.srec: u-boot.elf FORCE
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$(call if_changed,zobjcopy)
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@@ -918,6 +918,13 @@ dtb-$(CONFIG_RZA1) += \
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r7s72100-genmai.dtb \
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r7s72100-gr-peach.dtb
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dtb-$(CONFIG_RCAR_GEN5) += \
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r8a78000-ironhide.dtb
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ifdef CONFIG_RCAR_GEN5
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DTC_FLAGS += -R 4 -p 0x1000
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endif
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dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
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dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
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@@ -0,0 +1,8 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source extras for U-Boot for the Ironhide board
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include "r8a78000-u-boot.dtsi"
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@@ -0,0 +1,257 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Ironhide board
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a78000.dtsi"
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#include <dt-bindings/net/ti-dp83869.h>
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/ {
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model = "Renesas Ironhide board based on r8a78000";
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compatible = "renesas,ironhide", "renesas,r8a78000";
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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mmc0 = &mmc0;
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serial0 = &hscif0;
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};
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chosen {
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stdout-path = "serial0:1843200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x80000000>;
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};
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memory@1080000000 {
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device_type = "memory";
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reg = <0x10 0x80000000 0x0 0x80000000>;
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};
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memory@1200000000 {
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device_type = "memory";
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reg = <0x12 0x00000000 0x1 0x00000000>;
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};
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memory@1400000000 {
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device_type = "memory";
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reg = <0x14 0x00000000 0x1 0x00000000>;
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};
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memory@1600000000 {
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device_type = "memory";
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reg = <0x16 0x00000000 0x1 0x00000000>;
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};
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memory@1800000000 {
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device_type = "memory";
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reg = <0x18 0x00000000 0x1 0x00000000>;
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};
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memory@1a00000000 {
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device_type = "memory";
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reg = <0x1a 0x00000000 0x1 0x00000000>;
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};
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memory@1c00000000 {
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device_type = "memory";
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reg = <0x1c 0x00000000 0x1 0x00000000>;
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};
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memory@1e00000000 {
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device_type = "memory";
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reg = <0x1e 0x00000000 0x1 0x00000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&extal_clk {
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clock-frequency = <16666600>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&hscif0 {
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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eeprom@50 {
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compatible = "rohm,br24g01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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ð_pcs {
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phys = <&mp_phy 2 1>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-0 = <&mmc0_pins>;
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pinctrl-1 = <&mmc0_pins>;
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pinctrl-names = "default", "state_uhs";
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bus-width = <8>;
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full-pwr-cycle-in-suspend;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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status = "okay";
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};
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&ufs0 {
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status = "okay";
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};
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&ufs1 {
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status = "okay";
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};
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&mp_phy {
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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eth25g2_pins: eth25g2 {
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groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
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function = "eth25g2";
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drive-strength = <24>;
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};
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ethes0_pins: ethes0 {
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groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
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function = "ethes0";
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drive-strength = <24>;
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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mmc0_pins: mmc0 {
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groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
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function = "mmc0";
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drive-strength = <24>;
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};
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rsw3_pins: rsw3 {
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groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
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function = "rsw3";
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drive-strength = <24>;
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};
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scif_clk_pins: scif-clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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};
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&rswitch3 {
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pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>;
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pinctrl-names = "default";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* NOTE: Only port@4 is configured for R-Car X5H board.
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* Other ports (0-3, 5-12) are currently unused or not
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* connected.
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*/
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port@4 {
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reg = <4>;
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renesas,connect_to_xpcs;
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phy-handle = <&dp83869_phy>;
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phy-mode = "sgmii";
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phys = <ð_pcs 5>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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dp83869_phy: ethernet-phy@2 {
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reg = <2>;
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ti,sgmii-interface;
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ti,max-output-impedance;
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ti,refclk-output-enable;
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ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
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};
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};
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};
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};
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};
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&scif_clk {
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clock-frequency = <26000000>;
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};
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@@ -0,0 +1,139 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source extras for U-Boot on R-Car R8A78000 SoC
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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/ {
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soc {
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bootph-all;
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};
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/* Placeholder clock until the clock provider is in place */
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clk_stub_gpio: clk-stub-gpio {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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};
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clk_stub_i2c0: clk-stub-i2c0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <150000000>;
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};
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clk_stub_i2c1: clk-stub-i2c1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133333333>;
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};
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clk_stub_mmc: clk-stub-mmc {
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compatible = "renesas,compound-clock";
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#clock-cells = <0>;
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clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>,
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<&scmi_clk 1691>;
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clock-names = "mdlc", "per";
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};
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||||
};
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&cpg {
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bootph-all;
|
||||
};
|
||||
|
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&extal_clk {
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bootph-all;
|
||||
};
|
||||
|
||||
&extalr_clk {
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bootph-all;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
clocks = <&clk_stub_gpio>;
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||||
};
|
||||
|
||||
&gpio1 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio8 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio9 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio10 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clocks = <&clk_stub_i2c0>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
clocks = <&clk_stub_mmc>;
|
||||
};
|
||||
|
||||
&prr {
|
||||
bootph-all;
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -46,6 +46,11 @@ config RCAR_GEN4
|
||||
select RCAR_64
|
||||
select PINCTRL_PFC
|
||||
|
||||
config RCAR_GEN5
|
||||
bool "Renesas ARM SoCs R-Car Gen5 (64bit)"
|
||||
select RCAR_64
|
||||
select PINCTRL_PFC
|
||||
|
||||
config RZA1
|
||||
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
|
||||
select CPU_V7A
|
||||
|
||||
@@ -8,5 +8,6 @@ config OF_LIBFDT_OVERLAY
|
||||
|
||||
source "arch/arm/mach-renesas/Kconfig.rcar3"
|
||||
source "arch/arm/mach-renesas/Kconfig.rcar4"
|
||||
source "arch/arm/mach-renesas/Kconfig.rcar5"
|
||||
|
||||
endif
|
||||
|
||||
@@ -0,0 +1,26 @@
|
||||
if RCAR_GEN5
|
||||
|
||||
menu "Select Target SoC"
|
||||
|
||||
config R8A78000
|
||||
bool "Renesas SoC R8A78000"
|
||||
select GICV3
|
||||
imply PINCTRL_PFC_R8A78000
|
||||
|
||||
endmenu
|
||||
|
||||
choice
|
||||
prompt "Renesas ARM64 SoCs board select"
|
||||
optional
|
||||
|
||||
config TARGET_IRONHIDE
|
||||
bool "Ironhide board"
|
||||
imply R8A78000
|
||||
help
|
||||
Support for Renesas R-Car Gen5 Ironhide platform
|
||||
|
||||
endchoice
|
||||
|
||||
source "board/renesas/ironhide/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -12,6 +12,7 @@ obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
|
||||
obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
|
||||
obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o
|
||||
obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o
|
||||
obj-$(CONFIG_RCAR_GEN5) += cpu_info-rcar.o memmap-gen3.o
|
||||
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
|
||||
obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o
|
||||
|
||||
|
||||
@@ -15,8 +15,12 @@
|
||||
|
||||
static u32 renesas_get_prr(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_RCAR_64))
|
||||
return readl(0xFFF00044);
|
||||
if (IS_ENABLED(CONFIG_RCAR_64)) {
|
||||
if (IS_ENABLED(CONFIG_RCAR_GEN5))
|
||||
return readl(0x189E0044);
|
||||
else
|
||||
return readl(0xFFF00044);
|
||||
}
|
||||
|
||||
return readl(0xFF000044);
|
||||
}
|
||||
|
||||
@@ -72,6 +72,7 @@ static const struct {
|
||||
{ RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" },
|
||||
{ RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" },
|
||||
{ RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" },
|
||||
{ RMOBILE_CPU_TYPE_R8A78000, "R8A78000" },
|
||||
{ 0x0, "CPU" },
|
||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_RCAR_GEN5_BASE_H
|
||||
#define __ASM_ARCH_RCAR_GEN5_BASE_H
|
||||
|
||||
/*
|
||||
* R-Car (R8A78000) I/O Addresses
|
||||
*/
|
||||
#define TMU_BASE 0x1C030000
|
||||
|
||||
/* Arm Generic Timer */
|
||||
#define CNTCR_BASE 0x1C000FFF /* Region 0 */
|
||||
#define CNTFID0 (CNTCR_BASE + 0x020)
|
||||
#define CNTCR_EN BIT(0)
|
||||
|
||||
/* Reset */
|
||||
#define RST_BASE 0xC1320000 /* Domain0 */
|
||||
#define RST_SWSRES1A (RST_BASE + 0x410)
|
||||
#define RST_WDTRSTCR (RST_BASE + 0x420)
|
||||
#define RST_RWDT_RSTMSK BIT(0)
|
||||
#define RST_WWDT_RSTMSK BIT(2)
|
||||
#define RST_RESKCPROT0 (RST_BASE + 0x4F0)
|
||||
#define RST_KCPROT_DIS 0xA5A5A501
|
||||
|
||||
/* GICv4 */
|
||||
/* Distributor Registers */
|
||||
#define GICD_BASE 0x38000000
|
||||
#define GICR_BASE (GICR_LPI_BASE)
|
||||
|
||||
/* ReDistributor Registers for Control and Physical LPIs */
|
||||
#define GICR_LPI_BASE 0x38080000
|
||||
#define GICR_WAKER 0x0014
|
||||
#define GICR_PWRR 0x0024
|
||||
#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
|
||||
#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
|
||||
|
||||
/* ReDistributor Registers for SGIs and PPIs */
|
||||
#define GICR_SGI_BASE 0x38090000
|
||||
#define GICR_IGROUPR0 0x0080
|
||||
|
||||
#endif /* __ASM_ARCH_RCAR_GEN5_BASE_H */
|
||||
@@ -16,6 +16,8 @@
|
||||
#include <asm/arch/rcar-gen3-base.h>
|
||||
#elif defined(CONFIG_RCAR_GEN4)
|
||||
#include <asm/arch/rcar-gen4-base.h>
|
||||
#elif defined(CONFIG_RCAR_GEN5)
|
||||
#include <asm/arch/rcar-gen5-base.h>
|
||||
#elif defined(CONFIG_R7S72100)
|
||||
#elif defined(CONFIG_RZG2L)
|
||||
#include <asm/arch/rzg2l.h>
|
||||
@@ -42,6 +44,7 @@
|
||||
#define RENESAS_CPU_TYPE_R8A779F0 0x5A
|
||||
#define RENESAS_CPU_TYPE_R8A779G0 0x5C
|
||||
#define RENESAS_CPU_TYPE_R8A779H0 0x5D
|
||||
#define RMOBILE_CPU_TYPE_R8A78000 0x60
|
||||
#define RENESAS_CPU_TYPE_R9A07G044L 0x9A070440
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@@ -32,7 +32,12 @@ u32 __secure psci_version(void)
|
||||
|
||||
void __secure __noreturn psci_system_reset(void)
|
||||
{
|
||||
#if defined(CONFIG_RCAR_GEN5)
|
||||
writel(RST_KCPROT_DIS, RST_RESKCPROT0);
|
||||
writel(0x1, RST_SWSRES1A);
|
||||
#else
|
||||
writel(RST_SPRES, RST_SRESCR0);
|
||||
#endif
|
||||
|
||||
while (1)
|
||||
;
|
||||
|
||||
@@ -72,6 +72,7 @@ SECTIONS
|
||||
|
||||
__u_boot_list : {
|
||||
KEEP(*(SORT(__u_boot_list*)));
|
||||
. = ALIGN(8);
|
||||
} >ram
|
||||
|
||||
PROVIDE (__init_end = .);
|
||||
@@ -83,7 +84,7 @@ SECTIONS
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
. = ALIGN(8);
|
||||
} >ram
|
||||
PROVIDE (bss_end = .);
|
||||
PROVIDE (__bss_end = .);
|
||||
|
||||
@@ -6,7 +6,7 @@ N: grpeach
|
||||
N: r2dplus
|
||||
N: r7s72100
|
||||
N: r8a66597
|
||||
N: r8a77
|
||||
N: r8a7[78]
|
||||
N: r9a0[0-9]g
|
||||
N: rcar
|
||||
N: renesas
|
||||
|
||||
@@ -43,6 +43,10 @@ else
|
||||
obj-y += gen4-common.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef CONFIG_RCAR_GEN5
|
||||
obj-y += gen5-common.o
|
||||
endif
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
@@ -0,0 +1,75 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <asm/arch/renesas.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/system.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void init_generic_timer(void)
|
||||
{
|
||||
const u32 freq = CONFIG_SYS_CLK_FREQ;
|
||||
|
||||
/* Update memory mapped and register based freqency */
|
||||
asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
|
||||
writel(freq, CNTFID0);
|
||||
|
||||
/* Enable counter */
|
||||
setbits_le32(CNTCR_BASE, CNTCR_EN);
|
||||
}
|
||||
|
||||
static void init_gic_v3(void)
|
||||
{
|
||||
/* GIC v3 power on */
|
||||
writel(BIT(1), GICR_LPI_PWRR);
|
||||
|
||||
/* Wait till the WAKER_CA_BIT changes to 0 */
|
||||
clrbits_le32(GICR_LPI_WAKER, BIT(1));
|
||||
while (readl(GICR_LPI_WAKER) & BIT(2))
|
||||
;
|
||||
|
||||
writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
if (current_el() == 3)
|
||||
init_generic_timer();
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Allow WDT reset */
|
||||
writel(RST_KCPROT_DIS, RST_RESKCPROT0);
|
||||
clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK);
|
||||
|
||||
if (current_el() != 3)
|
||||
return 0;
|
||||
init_gic_v3();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __weak reset_cpu(void)
|
||||
{
|
||||
writel(RST_KCPROT_DIS, RST_RESKCPROT0);
|
||||
writel(0x1, RST_SWSRES1A);
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
if TARGET_IRONHIDE
|
||||
|
||||
config SYS_SOC
|
||||
default "renesas"
|
||||
|
||||
config SYS_BOARD
|
||||
default "ironhide"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "renesas"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "ironhide"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,43 @@
|
||||
#include <configs/renesas_rcar5.config>
|
||||
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RENESAS=y
|
||||
CONFIG_RCAR_GEN5=y
|
||||
CONFIG_TARGET_IRONHIDE=y
|
||||
|
||||
# CONFIG_OF_UPSTREAM is not set
|
||||
CONFIG_ARMV8_PSCI=y
|
||||
CONFIG_ARM_SMCCC=y
|
||||
CONFIG_BAUDRATE=1843200
|
||||
CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide"
|
||||
CONFIG_CLK_CCF=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_SCMI=y
|
||||
CONFIG_CMD_UFS=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_MMC_DEVICE_INDEX=0
|
||||
CONFIG_ENV_MMC_EMMC_HW_PARTITION=2
|
||||
CONFIG_ENV_OFFSET=0xFFFE0000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_FIRMWARE=y
|
||||
CONFIG_NR_DRAM_BANKS=16
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_RCAR_MFIS_MBOX=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_SCMI_AGENT_MAILBOX=y
|
||||
CONFIG_SCMI_FIRMWARE=y
|
||||
CONFIG_SCMI_POWER_DOMAIN=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_SYS_BARGSIZE=2048
|
||||
CONFIG_SYS_BOOT_GET_CMDLINE=y
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_CLK_FREQ=1066666667
|
||||
CONFIG_UFS=y
|
||||
CONFIG_UFS_RENESAS_GEN5=y
|
||||
@@ -0,0 +1,23 @@
|
||||
#include <configs/renesas_rcar64.config>
|
||||
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x9E600000
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
|
||||
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
# CONFIG_MMC_HS200_SUPPORT is not set
|
||||
# CONFIG_MMC_IO_VOLTAGE is not set
|
||||
# CONFIG_MMC_UHS_SUPPORT is not set
|
||||
CONFIG_PHY_R8A78000_ETHERNET_PCS=y
|
||||
CONFIG_PHY_R8A78000_MP_PHY=y
|
||||
CONFIG_PHY_TI_DP83869=y
|
||||
# CONFIG_PSCI_RESET is not set
|
||||
CONFIG_RENESAS_ETHER_SWITCH=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
@@ -26,3 +26,7 @@ obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
|
||||
obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
|
||||
|
||||
# Temporary stub clock used for SCP compatibility.
|
||||
# This is going to be removed once SCP solidifies.
|
||||
obj-$(CONFIG_R8A78000) += compound-clock.o
|
||||
|
||||
@@ -0,0 +1,92 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY UCLASS_CLK
|
||||
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <log.h>
|
||||
|
||||
struct clk_compound_rate {
|
||||
struct clk clk; /* This clock */
|
||||
struct clk mdlc; /* MDLC parent module clock */
|
||||
struct clk per; /* Peripheral parent clock */
|
||||
};
|
||||
|
||||
static struct clk_compound_rate *to_clk_compound_rate(struct clk *clk)
|
||||
{
|
||||
return (struct clk_compound_rate *)dev_get_plat(clk->dev);
|
||||
}
|
||||
|
||||
static int clk_compound_rate_enable(struct clk *clk)
|
||||
{
|
||||
struct clk_compound_rate *cc = to_clk_compound_rate(clk);
|
||||
|
||||
return clk_enable(&cc->mdlc);
|
||||
}
|
||||
|
||||
static int clk_compound_rate_disable(struct clk *clk)
|
||||
{
|
||||
struct clk_compound_rate *cc = to_clk_compound_rate(clk);
|
||||
|
||||
return clk_disable(&cc->mdlc);
|
||||
}
|
||||
|
||||
static ulong clk_compound_rate_get_rate(struct clk *clk)
|
||||
{
|
||||
struct clk_compound_rate *cc = to_clk_compound_rate(clk);
|
||||
|
||||
return clk_get_rate(&cc->per);
|
||||
}
|
||||
|
||||
static ulong clk_compound_rate_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
return 0; /* Set rate is not forwarded to SCP */
|
||||
}
|
||||
|
||||
const struct clk_ops clk_compound_rate_ops = {
|
||||
.enable = clk_compound_rate_enable,
|
||||
.disable = clk_compound_rate_disable,
|
||||
.get_rate = clk_compound_rate_get_rate,
|
||||
.set_rate = clk_compound_rate_set_rate,
|
||||
};
|
||||
|
||||
static int clk_compound_rate_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct clk_compound_rate *cc = (struct clk_compound_rate *)dev_get_plat(dev);
|
||||
struct clk *clk = &cc->clk;
|
||||
int ret;
|
||||
|
||||
clk->dev = dev;
|
||||
clk->id = CLK_ID(dev, 0);
|
||||
clk->enable_count = 0;
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &cc->mdlc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_get_by_index(dev, 1, &cc->per);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id clk_compound_rate_match[] = {
|
||||
{ .compatible = "renesas,compound-clock", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(renesas_compound_clock) = {
|
||||
.name = "compound-clock",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = clk_compound_rate_match,
|
||||
.of_to_plat = clk_compound_rate_of_to_plat,
|
||||
.plat_auto = sizeof(struct clk_compound_rate),
|
||||
.ops = &clk_compound_rate_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
@@ -66,6 +66,16 @@ config K3_SEC_PROXY
|
||||
Select this driver if your platform has support for this hardware
|
||||
block.
|
||||
|
||||
config RCAR_MFIS_MBOX
|
||||
bool "Renesas MFIS Multifunctional Interface mailbox driver"
|
||||
depends on DM_MAILBOX && ARCH_RENESAS
|
||||
help
|
||||
This enables support for the Renesas MFIS mailbox module, which
|
||||
provides an interface between the different CPU Cores, such as AP
|
||||
System Core domain and the Realtime Core domain, SCP Core domain
|
||||
and AP System Core domain or Realtime Core domain and AP System
|
||||
Core domain or Realtime Core domain.
|
||||
|
||||
config ZYNQMP_IPI
|
||||
bool "Xilinx ZynqMP IPI controller support"
|
||||
depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
|
||||
|
||||
@@ -12,4 +12,5 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
|
||||
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
|
||||
obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o
|
||||
obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o
|
||||
obj-$(CONFIG_RCAR_MFIS_MBOX) += renesas-mfis.o
|
||||
obj-$(CONFIG_ZYNQMP_IPI) += zynqmp-ipi.o
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2020-2025, Renesas Electronics Corporation.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <mailbox-uclass.h>
|
||||
|
||||
#define COM 0x0
|
||||
#define IIR BIT(0)
|
||||
|
||||
struct mfis_priv {
|
||||
void __iomem *tx_base;
|
||||
};
|
||||
|
||||
static int mfis_send(struct mbox_chan *chan, const void *data)
|
||||
{
|
||||
struct mfis_priv *mfis = dev_get_priv(chan->dev);
|
||||
|
||||
writel(IIR, mfis->tx_base + COM);
|
||||
|
||||
/* Give the remote side some time. */
|
||||
mdelay(1);
|
||||
|
||||
writel(0, mfis->tx_base + COM);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct mbox_ops mfis_mbox_ops = {
|
||||
.send = mfis_send,
|
||||
};
|
||||
|
||||
static int mfis_mbox_probe(struct udevice *dev)
|
||||
{
|
||||
struct mfis_priv *mbox = dev_get_priv(dev);
|
||||
|
||||
mbox->tx_base = dev_read_addr_index_ptr(dev, 0);
|
||||
if (!mbox->tx_base)
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id mfis_mbox_of_match[] = {
|
||||
{ .compatible = "renesas,mfis-mbox", },
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(renesas_mfis) = {
|
||||
.name = "renesas-mfis",
|
||||
.id = UCLASS_MAILBOX,
|
||||
.of_match = mfis_mbox_of_match,
|
||||
.probe = mfis_mbox_probe,
|
||||
.priv_auto = sizeof(struct mfis_priv),
|
||||
.ops = &mfis_mbox_ops,
|
||||
};
|
||||
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __IRONHIDE_H
|
||||
#define __IRONHIDE_H
|
||||
|
||||
#include "rcar-gen5-common.h"
|
||||
|
||||
#endif /* __IRONHIDE_H */
|
||||
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __RCAR_GEN5_COMMON_H
|
||||
#define __RCAR_GEN5_COMMON_H
|
||||
|
||||
#include <asm/arch/renesas.h>
|
||||
|
||||
/* Console */
|
||||
#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 }
|
||||
|
||||
/* Memory */
|
||||
#define DRAM_RSV_SIZE 0x08000000
|
||||
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
|
||||
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
|
||||
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
|
||||
|
||||
/* Environment setting */
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"bootm_size=0x10000000\0"
|
||||
|
||||
#endif /* __RCAR_GEN5_COMMON_H */
|
||||
@@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*
|
||||
* IDs match SCP 4.27
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
|
||||
#define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__
|
||||
|
||||
/*
|
||||
* These definition indices match the Clock ID defined by SCP FW 4.27.
|
||||
*/
|
||||
|
||||
#define SCP_CLOCK_ID_MDLC_UFS0 202
|
||||
#define SCP_CLOCK_ID_MDLC_UFS1 203
|
||||
#define SCP_CLOCK_ID_MDLC_SDHI0 204
|
||||
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS0 316
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS1 317
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS2 318
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS3 319
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS4 320
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS5 321
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS6 322
|
||||
#define SCP_CLOCK_ID_MDLC_XPCS7 323
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3 324
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSN 325
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3AES 326
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES0 327
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES1 328
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES2 329
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES3 330
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES4 331
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES5 332
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES6 333
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3TSNTES7 334
|
||||
#define SCP_CLOCK_ID_MDLC_RSW3MFWD 335
|
||||
|
||||
#define SCP_CLOCK_ID_MDLC_MPPHY01 344
|
||||
#define SCP_CLOCK_ID_MDLC_MPPHY11 345
|
||||
#define SCP_CLOCK_ID_MDLC_MPPHY21 346
|
||||
#define SCP_CLOCK_ID_MDLC_MPPHY31 347
|
||||
#define SCP_CLOCK_ID_MDLC_MPPHY02 348
|
||||
|
||||
#endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*
|
||||
* IDs match SCP 4.27
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_R8A78000_SCMI_POWER_H__
|
||||
#define __DT_BINDINGS_R8A78000_SCMI_POWER_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the Power Domain ID defined by SCP FW 4.27.
|
||||
*/
|
||||
|
||||
#define X5H_POWER_DOMAIN_ID_UFS0 12
|
||||
#define X5H_POWER_DOMAIN_ID_UFS1 13
|
||||
|
||||
#define X5H_POWER_DOMAIN_ID_RSW 15
|
||||
|
||||
#define X5H_POWER_DOMAIN_ID_MPP0 17
|
||||
#define X5H_POWER_DOMAIN_ID_MPP1 18
|
||||
#define X5H_POWER_DOMAIN_ID_MPP2 19
|
||||
#define X5H_POWER_DOMAIN_ID_MPP3 20
|
||||
|
||||
#endif /* __DT_BINDINGS_R8A78000_SCMI_POWER_H__ */
|
||||
@@ -0,0 +1,33 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*
|
||||
* IDs match SCP 4.27
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__
|
||||
#define __DT_BINDINGS_R8A78000_SCMI_RESET_H__
|
||||
|
||||
/*
|
||||
* These definition indices match the Reset ID defined by SCP FW 4.27.
|
||||
*/
|
||||
|
||||
#define SCP_RESET_DOMAIN_ID_UFS0 202
|
||||
#define SCP_RESET_DOMAIN_ID_UFS1 203
|
||||
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS0 316
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS1 317
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS2 318
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS3 319
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS4 320
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS5 321
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS6 322
|
||||
#define SCP_RESET_DOMAIN_ID_XPCS7 323
|
||||
|
||||
#define SCP_RESET_DOMAIN_ID_MPPHY01 344
|
||||
#define SCP_RESET_DOMAIN_ID_MPPHY11 345
|
||||
#define SCP_RESET_DOMAIN_ID_MPPHY21 346
|
||||
#define SCP_RESET_DOMAIN_ID_MPPHY31 347
|
||||
#define SCP_RESET_DOMAIN_ID_MPPHY02 348
|
||||
|
||||
#endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */
|
||||
Reference in New Issue
Block a user