vhaudiquet/u-boot-krane
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drivers: ddr: altera: Correct DDR calibration status check

Browse Source 
Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Naresh Kumar Ravulapalli
2025-09-30 14:29:53 +08:00
committed by Tien Fong Chee
parent 5d2ef97c66
commit 63ef1c7a73
2 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/ddr/altera/sdram_soc64.c
+3 -3
View File
@@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat)
debug("DDR: Triggerring emif reset\n");
hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
/* if seq2core[3] = 0, we are good */
/* if seq2core[2:0] = 0b0000_0111, we are good */
ret = wait_for_bit_le32((const void *)(plat->hmc +
RSTHANDSHAKESTAT),
DDR_HMC_SEQ2CORE_INT_RESP_MASK,
false, 1000, false);
DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK,
true, 1000, false);
if (ret) {
printf("DDR: failed to get ack from EMIF\n");
return ret;
drivers/ddr/altera/sdram_soc64.h
+1 -1
View File
@@ -77,7 +77,7 @@ struct altera_sdram_plat {
#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f
#define DDR_HMC_CORE2SEQ_INT_REQ 0x0000000f
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK GENMASK(2, 0)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
#define DDR_HMC_ERRINTEN_INTMASK \