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Merge branch '2023-10-31-platform-updates'

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- Updates for npcm8xx, developerbox, corstone1000 and one clock fix for
  TI K3 platforms.
This commit is contained in:
Tom Rini
2023-10-31 13:08:10 -04:00
parent cbba1b7766 edf90d4e73
commit 62fc66b6d2
10 changed files with 111 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files
board/nuvoton/arbel_evb/arbel_evb.c
+19 -20
View File
@@ -16,7 +16,7 @@
#define DRAM_1GB_SIZE 0x40000000ULL
#define DRAM_2GB_ECC_SIZE 0x70000000ULL
#define DRAM_2GB_SIZE 0x80000000ULL
#define DRAM_4GB_ECC_SIZE 0xE00000000ULL
#define DRAM_4GB_ECC_SIZE 0xE0000000ULL
#define DRAM_4GB_SIZE 0x100000000ULL
DECLARE_GLOBAL_DATA_PTR;
@@ -29,7 +29,6 @@ int board_init(void)
int dram_init(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
uint64_t delta = 0ULL;
/*
* get dram active size value from bootblock.
@@ -38,17 +37,21 @@ int dram_init(void)
*/
gd->ram_size = readl(&gcr->scrpad_c);
debug("%s: scrpad_c: %llx ", __func__, gd->ram_size);
if (gd->ram_size == 0) {
if (gd->ram_size == 0)
gd->ram_size = readl(&gcr->scrpad_b);
debug("%s: scrpad_b: %llx ", __func__, gd->ram_size);
} else {
else
gd->ram_size *= 0x100000ULL;
}
debug("ram_size: %llx ", gd->ram_size);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0;
debug("ram_size: %llx ", gd->ram_size);
switch (gd->ram_size) {
case DRAM_512MB_ECC_SIZE:
@@ -62,32 +65,28 @@ int dram_init(void)
gd->bd->bi_dram[1].size = 0;
break;
case DRAM_4GB_ECC_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE;
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
/* use bank0 only */
gd->ram_size = DRAM_2GB_SIZE;
break;
case DRAM_4GB_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE;
/* use bank0 only */
gd->ram_size = DRAM_2GB_SIZE;
break;
default:
gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
gd->ram_size = DRAM_1GB_SIZE;
break;
}
gd->ram_size -= delta;
return 0;
}
int dram_init_banksize(void)
{
dram_init();
return 0;
}
configs/arbel_evb_defconfig
+1
View File
@@ -58,6 +58,7 @@ CONFIG_MMC_SDHCI_NPCM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
configs/corstone1000_defconfig
+2 -1
View File
@@ -14,7 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
CONFIG_CONSOLE_RECORD=y
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_CPUINFO is not set
@@ -55,6 +55,7 @@ CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
doc/board/socionext/developerbox.rst
+4 -3
View File
@@ -42,9 +42,10 @@ Compile from source
You can build U-Boot without any additinal source code.::
cd u-boot
git checkout v2023.07
export ARCH=arm64
export CROSS_COMPILE=aarch64-linux-gnu-
make SynQuacer_defconfig
make synquacer_developerbox_defconfig
make -j `noproc`
Then, expand the binary to 1MB for preparing flash.::
@@ -211,8 +212,8 @@ can be installed via NOR flash writer.
Once the flasher tool is running we are ready to flash the images.::
Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.::
flash rawwrite 600000 180000
flash rawwrite a00000 180000
flash rawwrite 600000 400000
flash rawwrite a00000 400000
>> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) <<
flash rawwrite 500000 1000
drivers/clk/ti/clk-k3-pll.c
+75 -6
View File
@@ -25,6 +25,23 @@
#define PLL_16FFT_FREQ_CTRL0 0x30
#define PLL_16FFT_FREQ_CTRL1 0x34
#define PLL_16FFT_DIV_CTRL 0x38
#define PLL_16FFT_CAL_CTRL 0x60
#define PLL_16FFT_CAL_STAT 0x64
/* CAL STAT register bits */
#define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31)
/* CFG register bits */
#define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0)
#define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0)
#define PLL_16FFT_CFG_PLL_TYPE_FRACF 1
/* CAL CTRL register bits */
#define PLL_16FFT_CAL_CTRL_CAL_EN BIT(31)
#define PLL_16FFT_CAL_CTRL_FAST_CAL BIT(20)
#define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15)
#define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16
#define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16)
/* CTRL register bits */
#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
@@ -40,9 +57,14 @@
/* DIV CTRL register bits */
#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f
#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
/* HSDIV register bits*/
#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
/* FREQ_CTRL1 bits */
#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff
#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0
/* KICK register magic values */
#define PLL_KICK0_VALUE 0x68ef3490
#define PLL_KICK1_VALUE 0xd172bc5a
@@ -63,18 +85,65 @@ static int ti_pll_wait_for_lock(struct clk *clk)
{
struct ti_pll_clk *pll = to_clk_pll(clk);
u32 stat;
u32 cfg;
u32 cal;
u32 freq_ctrl1;
int i;
u32 pllfm;
u32 pll_type;
int success;
for (i = 0; i < 100000; i++) {
stat = readl(pll->reg + PLL_16FFT_STAT);
if (stat & PLL_16FFT_STAT_LOCK)
return 0;
if (stat & PLL_16FFT_STAT_LOCK) {
success = 1;
break;
}
}
printf("%s: pll (%s) failed to lock\n", __func__,
clk->dev->name);
/* Enable calibration if not in fractional mode of the FRACF PLL */
freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK;
pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT;
cfg = readl(pll->reg + PLL_16FFT_CFG);
pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT;
return -EBUSY;
if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) {
cal = readl(pll->reg + PLL_16FFT_CAL_CTRL);
/* Enable calibration for FRACF */
cal |= PLL_16FFT_CAL_CTRL_CAL_EN;
/* Enable fast cal mode */
cal |= PLL_16FFT_CAL_CTRL_FAST_CAL;
/* Disable calibration bypass */
cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP;
/* Set CALCNT to 2 */
cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK;
cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT;
/* Note this register does not readback the written value. */
writel(cal, pll->reg + PLL_16FFT_CAL_CTRL);
success = 0;
for (i = 0; i < 100000; i++) {
stat = readl(pll->reg + PLL_16FFT_CAL_STAT);
if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) {
success = 1;
break;
}
}
}
if (success == 0) {
printf("%s: pll (%s) failed to lock\n", __func__,
clk->dev->name);
return -EBUSY;
} else {
return 0;
}
}
static ulong ti_pll_clk_get_rate(struct clk *clk)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+1
View File
@@ -329,6 +329,7 @@ struct group_info {
static const struct group_info npcm8xx_groups[] = {
FUNC_LIST
{FN_gpio, "GPIO", NULL, 0, 0, 0}
};
/* Pin flags */
include/configs/arbel.h
+5 -1
View File
@@ -7,11 +7,15 @@
#define __CONFIG_ARBEL_H
#define CFG_SYS_SDRAM_BASE 0x0
#define CFG_SYS_BOOTMAPSZ (30 << 20)
#define CFG_SYS_BOOTMAPSZ (128 << 20)
#define CFG_SYS_BOOTM_LEN (20 << 20)
#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CFG_SYS_INIT_RAM_SIZE 0x8000
#define CFG_SYS_BAUDRATE_TABLE \
{ 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \
"stdin=serial\0" \
include/configs/corstone1000.h
+2 -1
View File
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2022 ARM Limited
* Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
* (C) Copyright 2022 Linaro
* Rui Miguel Silva <rui.silva@linaro.org>
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
@@ -29,5 +29,6 @@
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS BOOTENV
#endif
include/configs/poleg.h
+2
View File
@@ -13,6 +13,8 @@
#define CFG_SYS_BOOTMAPSZ (0x30 << 20)
#define CFG_SYS_SDRAM_BASE 0x0
#define CFG_SYS_BAUDRATE_TABLE { 57600, 115200, 230400, 460800 }
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
"stdin=serial\0" \
include/configs/synquacer.h
-19
View File
@@ -40,20 +40,6 @@
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
#define DEFAULT_DFU_ALT_INFO
#else
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
"mtd nor1=u-boot.bin raw 200000 100000;" \
"fip.bin raw 180000 78000;" \
"optee.bin raw 500000 100000\0"
#endif
/* GUIDs for capsule updatable firmware images */
#define DEVELOPERBOX_UBOOT_IMAGE_GUID \
EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \
0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00)
#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
#define DEVELOPERBOX_FIP_IMAGE_GUID \
EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
@@ -64,10 +50,6 @@
0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
#endif
#define DEVELOPERBOX_OPTEE_IMAGE_GUID \
EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \
0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30)
/* Distro boot settings */
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
@@ -107,7 +89,6 @@
"ramdisk_addr_r=0xa0000000\0" \
"scriptaddr=0x88000000\0" \
"pxefile_addr_r=0x88100000\0" \
DEFAULT_DFU_ALT_INFO \
BOOTENV
#endif /* __CONFIG_H */