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clk: mediaTek: mt8195: add clock tree type flags

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Add clock tree type flags to the mt8195 clock tree structures. These
will be used later for parent lookup.

Link: https://patch.msgid.link/20260710-mtk-clk-parent-lookup-improvements-v2-13-f3f3a4a28dca@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner
2026-07-22 12:01:17 -05:00
parent 9ad117b8fc
commit 5c15fdc8e0
1 changed files with 4 additions and 0 deletions
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drivers/clk/mediatek/clk-mt8195.c
+4
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@@ -101,6 +101,7 @@ static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = {
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.plls = apmixed_plls,
.num_plls = ARRAY_SIZE(apmixed_plls),
.type = MTK_CLK_TREE_APMIXED,
};
#define FIXED_CLK0(_id, _rate) \
@@ -1423,6 +1424,7 @@ static const struct mtk_clk_tree mt8195_topckgen_clk_tree = {
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
.num_gates = ARRAY_SIZE(top_cg_clks),
.type = MTK_CLK_TREE_TOPCKGEN,
};
static const struct mtk_gate_regs infra_ao0_cg_regs = {
@@ -1635,6 +1637,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
.name = "mt8195-apmixedsys",
.id = UCLASS_CLK,
.of_match = mt8195_apmixed,
.bind = mtk_common_clk_parent_bind,
.probe = mt8195_apmixedsys_probe,
.priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_apmixedsys_ops,
@@ -1645,6 +1648,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
.name = "mt8195-topckgen",
.id = UCLASS_CLK,
.of_match = mt8195_topckgen_compat,
.bind = mtk_common_clk_parent_bind,
.probe = mt8195_topckgen_probe,
.priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,