arm64: versal2: Select GIC redistributor base at runtime

The GIC redistributor base address depends on the part: the 2VM3654
device has 4 APU cores and 3 GIC ITS blocks, which shifts the
redistributor region up compared to the base 8 core / single ITS part.
A single U-Boot binary must therefore pick the right base at runtime
instead of relying on the compile-time GICR_BASE used by the generic
lowlevel_init().

Add a SoC specific lowlevel_init() that reads the PMC TAP IDCODE and
selects GICR_BASE_2VM3654 for the 2VM3654 device, otherwise keeps the
default GICR_BASE. CONFIG_ARMV8_MULTIENTRY is not supported on Versal
Gen 2 so the generic slave handling is intentionally dropped.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/4c0dc2b6e29d300db15be0844879ab4d028d98a9.1783493630.git.michal.simek@amd.com

arch/arm/mach-versal2/Makefile

@@ -8,3 +8,4 @@
 
 obj-y	+= clk.o
 obj-y	+= cpu.o
+obj-y	+= lowlevel_init.o

arch/arm/mach-versal2/lowlevel_init.S

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * SoC specific lowlevel_init for AMD Versal Gen 2
+ *
+ * Copyright (C) 2026, Advanced Micro Devices, Inc.
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/arch/hardware.h>
+
+ENTRY(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+#if defined(CONFIG_GICV3)
+	branch_if_slave x0, 1f
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+	/*
+	 * Pick the redistributor base for this part. Default to GICR_BASE
+	 * and switch to GICR_BASE_2VM3654 when the PMC TAP IDCODE matches
+	 * the 2VM3654 device.
+	 */
+	ldr	x0, =GICR_BASE
+	ldr	x1, =PMC_TAP_IDCODE
+	ldr	w1, [x1]
+	ldr	w2, =GICR_IDCODE_2VM3654
+	cmp	w1, w2
+	b.ne	3f
+	ldr	x0, =GICR_BASE_2VM3654
+3:
+	bl	gic_init_secure_percpu
+#endif
+
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)

include/configs/amd_versal2.h

@@ -19,6 +19,15 @@
 #define GICD_BASE	0xe2000000
 #define GICR_BASE	0xe2060000
 
+/*
+ * The 2VM3654 part has 4 APU cores and 3 GIC ITS blocks (vs 8 cores and a
+ * single ITS on the base part), which moves the redistributor region up by
+ * the two extra ITS blocks. The right base is selected at runtime in
+ * lowlevel_init() based on the PMC TAP IDCODE.
+ */
+#define GICR_BASE_2VM3654	0xe20a0000
+#define GICR_IDCODE_2VM3654	0x04d98093
+
 /* Serial setup */
 #define CFG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }