arm: dts: k3-am64: Move to OF_UPSTREAM
Enable OF_UPSTREAM for AM64-EVM and SK-AM64 boards. Remove DT files that are now available in dts/upstream. Update the appended files based on version of latest OF_UPSTREAM sync point (v6.7-rc7). Signed-off-by: Andrew Davis <afd@ti.com>
This commit is contained in:
Andrew Davis
Tom Rini
@@ -1418,9 +1418,7 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
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dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
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k3-j784s4-r5-evm.dtb
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dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
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k3-am642-r5-evm.dtb \
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k3-am642-sk.dtb \
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dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
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k3-am642-r5-sk.dtb \
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k3-am642-phyboard-electra-rdk.dtb \
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k3-am642-r5-phycore-som-2gb.dtb
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File diff suppressed because it is too large
Load Diff
@@ -1,161 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM64 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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/*
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* The MCU domain timer interrupts are routed only to the ESM module,
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* and not currently available for Linux. The MCU domain timers are
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* of limited use without interrupts, and likely reserved by the ESM.
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*/
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mcu_timer0: timer@4800000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4800000 0x00 0x400>;
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clocks = <&k3_clks 35 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer1: timer@4810000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4810000 0x00 0x400>;
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clocks = <&k3_clks 48 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer2: timer@4820000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4820000 0x00 0x400>;
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clocks = <&k3_clks 49 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer3: timer@4830000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x4830000 0x00 0x400>;
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clocks = <&k3_clks 50 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_uart0: serial@4a00000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x04a00000 0x00 0x100>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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mcu_uart1: serial@4a10000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x04a10000 0x00 0x100>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 160 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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mcu_i2c0: i2c@4900000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x04900000 0x00 0x100>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 106 2>;
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clock-names = "fck";
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status = "disabled";
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};
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mcu_i2c1: i2c@4910000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x04910000 0x00 0x100>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 107 2>;
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clock-names = "fck";
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status = "disabled";
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};
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mcu_spi0: spi@4b00000 {
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compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
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reg = <0x00 0x04b00000 0x00 0x400>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 147 0>;
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status = "disabled";
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};
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mcu_spi1: spi@4b10000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x00 0x04b10000 0x00 0x400>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 148 0>;
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status = "disabled";
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};
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mcu_gpio_intr: interrupt-controller@4210000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x04210000 0x00 0x200>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <5>;
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ti,interrupt-ranges = <0 104 4>;
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};
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mcu_gpio0: gpio@4201000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x0 0x4201000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&mcu_gpio_intr>;
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interrupts = <30>, <31>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <23>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 79 0>;
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clock-names = "gpio";
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};
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mcu_pmx0: pinctrl@4084000 {
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compatible = "pinctrl-single";
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reg = <0x00 0x4084000 0x00 0x84>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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mcu_esm: esm@4100000 {
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compatible = "ti,j721e-esm";
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reg = <0x00 0x4100000 0x00 0x1000>;
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ti,esm-pins = <0>, <1>;
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};
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};
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@@ -1,33 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/thermal/thermal.h>
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thermal_zones: thermal-zones {
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main0_thermal: main0-thermal {
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polling-delay-passive = <250>; /* milliSeconds */
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polling-delay = <500>; /* milliSeconds */
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thermal-sensors = <&main_vtm0 0>;
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trips {
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main0_crit: main0-crit {
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temperature = <105000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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main1_thermal: main1-thermal {
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polling-delay-passive = <250>; /* milliSeconds */
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polling-delay = <500>; /* milliSeconds */
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thermal-sensors = <&main_vtm0 1>;
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trips {
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main1_crit: main1-crit {
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temperature = <105000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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};
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@@ -1,100 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM642 SoC Family
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include "k3-pinctrl.h"
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/ {
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model = "Texas Instruments K3 AM642 SoC";
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compatible = "ti,am642";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a53_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@f4000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
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<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
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<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
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<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
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<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
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<0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
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<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
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<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
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<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
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<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
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<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
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<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
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<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
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<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
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<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
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<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
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<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
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<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
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<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
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<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
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<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
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<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
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<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
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<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
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/* MCU Domain Range */
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<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
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cbass_mcu: bus@4000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
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};
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};
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#include "k3-am64-thermal.dtsi"
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};
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/* Now include the peripherals for each bus segments */
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#include "k3-am64-main.dtsi"
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#include "k3-am64-mcu.dtsi"
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@@ -9,97 +9,27 @@
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chosen {
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tick-timer = &main_timer0;
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};
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memory@80000000 {
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bootph-all;
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};
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};
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&cbass_main {
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bootph-all;
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};
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&main_timer0 {
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bootph-all;
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clock-frequency = <200000000>;
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};
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&main_conf {
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bootph-all;
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chipid@14 {
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bootph-all;
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};
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};
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&main_pmx0 {
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bootph-all;
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};
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&main_i2c0_pins_default {
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bootph-all;
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};
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&main_i2c0 {
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bootph-all;
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};
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&main_uart0_pins_default {
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bootph-all;
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};
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&main_uart0 {
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bootph-all;
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};
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&main_usb0_pins_default {
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bootph-all;
|
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};
|
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&usb0 {
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dr_mode="peripheral";
|
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bootph-all;
|
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};
|
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|
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&usbss0 {
|
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bootph-all;
|
||||
};
|
||||
|
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&main_mmc1_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_usb0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
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&dmss {
|
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bootph-all;
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};
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||||
|
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&secure_proxy_main {
|
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bootph-all;
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||||
};
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||||
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&dmsc {
|
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bootph-all;
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||||
k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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bootph-all;
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||||
};
|
||||
};
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||||
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&k3_pds {
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bootph-all;
|
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};
|
||||
|
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&k3_clks {
|
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bootph-all;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bootph-all;
|
||||
};
|
||||
@@ -108,10 +38,6 @@
|
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bootph-all;
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||||
};
|
||||
|
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&sdhci1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&inta_main_dmss {
|
||||
bootph-all;
|
||||
};
|
||||
@@ -143,42 +69,6 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&mdio1_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cpsw3g_phy0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&rgmii1_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&rgmii2_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
bootph-all;
|
||||
|
||||
ethernet-ports {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&phy_gmii_sel {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -1,690 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
#include "k3-serdes.h"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-evm", "ti,am642";
|
||||
model = "Texas Instruments AM642 EVM";
|
||||
|
||||
chosen {
|
||||
stdout-path = &main_uart0;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &mcu_uart0;
|
||||
serial1 = &main_uart1;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart3;
|
||||
i2c0 = &main_i2c0;
|
||||
i2c1 = &main_i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: regulator-0 {
|
||||
/* main DC jack */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: regulator-1 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: regulator-2 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-3 {
|
||||
/* TPS2051BD */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vddb: regulator-4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddb_3v3_display";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vtt_supply: regulator-5 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ddr_vtt_pins_default>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
label = "am64-evm:red:heartbeat";
|
||||
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
mdio_mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mdio-mux-1 {
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mdio_mux>;
|
||||
mdio-parent-bus = <&cpsw3g_mdio>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw3g_phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
transceiver1: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
transceiver2: can-phy1 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
||||
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
|
||||
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
|
||||
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_spi0_pins_default: main-spi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
|
||||
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
|
||||
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
|
||||
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb0_pins_default: main-usb0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_ecap0_pins_default: main-ecap0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan0_pins_default: main-mcan0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
|
||||
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan1_pins_default: main-mcan1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
|
||||
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
ddr_vtt_pins_default: ddr-vtt-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
&main_uart1 {
|
||||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@50 {
|
||||
/* AT24CM01 */
|
||||
compatible = "atmel,24c1024";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
|
||||
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
|
||||
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
|
||||
"MMC1_SD_EN", "FSI_FET_SEL",
|
||||
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
|
||||
"CPSW_FET_SEL", "CPSW_FET2_SEL",
|
||||
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
|
||||
"GPIO_OLED_RESETn", "VPP_LDO_EN",
|
||||
"TEST_LED1", "TP92", "TP90", "TP88",
|
||||
"TP87", "TP86", "TP89", "TP91";
|
||||
};
|
||||
|
||||
/* osd9616p0899-10 */
|
||||
display@3c {
|
||||
compatible = "solomon,ssd1306fb-i2c";
|
||||
reg = <0x3c>;
|
||||
reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
|
||||
vbat-supply = <&vddb>;
|
||||
solomon,height = <16>;
|
||||
solomon,width = <96>;
|
||||
solomon,com-seq;
|
||||
solomon,com-invdir;
|
||||
solomon,page-offset = <0>;
|
||||
solomon,prechargep1 = <2>;
|
||||
solomon,prechargep2 = <13>;
|
||||
};
|
||||
};
|
||||
|
||||
/* mcu_gpio0 is reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
eeprom@0 {
|
||||
compatible = "microchip,93lc46b";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cs-high;
|
||||
data-size = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/* emmc */
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
ti,usb2-only;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb0_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default>;
|
||||
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
/* ADC is reserved for R5 usage */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x100000 0x200000>;
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x300000 0x400000>;
|
||||
};
|
||||
|
||||
partition@700000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x700000 0x40000>;
|
||||
};
|
||||
|
||||
partition@740000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x740000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
/* PWM is available on Pin 1 of header J12 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_ecap0_pins_default>;
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_pins_default>;
|
||||
phys = <&transceiver1>;
|
||||
};
|
||||
|
||||
&main_mcan1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan1_pins_default>;
|
||||
phys = <&transceiver2>;
|
||||
};
|
||||
@@ -40,10 +40,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&vtt_supply {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
@@ -53,18 +49,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&main_esm {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&mcu_esm {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&secure_proxy_main 0>,
|
||||
<&secure_proxy_main 1>,
|
||||
@@ -74,10 +58,6 @@
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&vtt_supply {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&memorycontroller {
|
||||
vtt-supply = <&vtt_supply>;
|
||||
};
|
||||
@@ -92,10 +72,6 @@
|
||||
clock-names = "clk_xin";
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
/* UART is initialized before SYSFW is started
|
||||
* so we can't do any power-domain/clock operations.
|
||||
* Delete clock/power-domain properties to avoid
|
||||
|
||||
@@ -49,18 +49,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&main_esm {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&mcu_esm {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&secure_proxy_main 0>,
|
||||
<&secure_proxy_main 1>,
|
||||
|
||||
@@ -9,87 +9,21 @@
|
||||
chosen {
|
||||
tick-timer = &main_timer0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_timer0 {
|
||||
bootph-all;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
&main_conf {
|
||||
bootph-all;
|
||||
chipid@14 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_i2c0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&dmss {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
bootph-all;
|
||||
k3_sysreset: sysreset-controller {
|
||||
compatible = "ti,sci-sysreset";
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&k3_pds {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&k3_reset {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "disabled";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_mmc1_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&inta_main_dmss {
|
||||
@@ -180,38 +114,10 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_usb0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_wiz0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes0_usb_link {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&serdes_refclk {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ospi0_pins_default {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@@ -1,642 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
#include "k3-serdes.h"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-sk", "ti,am642";
|
||||
model = "Texas Instruments AM642 SK";
|
||||
|
||||
chosen {
|
||||
stdout-path = &main_uart0;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &mcu_uart0;
|
||||
serial1 = &main_uart1;
|
||||
serial2 = &main_uart0;
|
||||
i2c0 = &main_i2c0;
|
||||
i2c1 = &main_i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: regulator-0 {
|
||||
/* USB MAIN INPUT 5V DC */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vusb_main5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: regulator-1 {
|
||||
/* output of LP8733xx */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vusb_main>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-2 {
|
||||
/* TPS2051BD */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
com8_ls_en: regulator-3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "com8_ls_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
pinctrl-0 = <&main_com8_ls_en_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan_en: regulator-4 {
|
||||
/* output of SN74AVC4T245RSVR */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wlan_en";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
enable-active-high;
|
||||
pinctrl-0 = <&main_wlan_en_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
vin-supply = <&com8_ls_en>;
|
||||
gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-controller {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <1>;
|
||||
gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-1 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <2>;
|
||||
gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <3>;
|
||||
gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <4>;
|
||||
gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <5>;
|
||||
gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-5 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <6>;
|
||||
gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-6 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <7>;
|
||||
gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-7 {
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
function-enumerator = <8>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
||||
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
|
||||
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
|
||||
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb0_pins_default: main-usb0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_ecap0_pins_default: main-ecap0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
main_wlan_en_pins_default: main-wlan-en-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_wlan_pins_default: main-wlan-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
status = "reserved";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@70 {
|
||||
compatible = "nxp,pca9538";
|
||||
reg = <0x70>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"PRU_DETECT", "MMC1_SD_EN",
|
||||
"VPP_LDO_EN", "RPI_PS_3V3_En",
|
||||
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
|
||||
};
|
||||
|
||||
exp2: gpio@60 {
|
||||
compatible = "ti,tpic2810";
|
||||
reg = <0x60>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
|
||||
};
|
||||
};
|
||||
|
||||
/* mcu_gpio0 is reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
vmmc-supply = <&wlan_en>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1837";
|
||||
reg = <2>;
|
||||
pinctrl-0 = <&main_wlan_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_USB>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_usb_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "host";
|
||||
maximum-speed = "super-speed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb0_pins_default>;
|
||||
phys = <&serdes0_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default>;
|
||||
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x100000 0x200000>;
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x300000 0x400000>;
|
||||
};
|
||||
|
||||
partition@700000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x700000 0x40000>;
|
||||
};
|
||||
|
||||
partition@740000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x740000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
/* PWM is available on Pin 1 of header J3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_ecap0_pins_default>;
|
||||
};
|
||||
@@ -1,66 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC family in Dual core configuration
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am64.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <256>;
|
||||
};
|
||||
};
|
||||
@@ -118,11 +118,11 @@
|
||||
|
||||
#ifdef CONFIG_TARGET_AM642_A53_EVM
|
||||
|
||||
#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
|
||||
#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
|
||||
#define SPL_AM642_EVM_DTB "spl/dts/ti/k3-am642-evm.dtb"
|
||||
#define SPL_AM642_SK_DTB "spl/dts/ti/k3-am642-sk.dtb"
|
||||
|
||||
#define AM642_EVM_DTB "u-boot.dtb"
|
||||
#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
|
||||
#define AM642_SK_DTB "dts/upstream/src/arm64/ti/k3-am642-sk.dtb"
|
||||
|
||||
&binman {
|
||||
ti-spl {
|
||||
|
||||
@@ -16,7 +16,7 @@ CONFIG_SF_DEFAULT_SPEED=25000000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-evm"
|
||||
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_DM_RESET=y
|
||||
@@ -74,7 +74,7 @@ CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="k3-am642-evm k3-am642-sk"
|
||||
CONFIG_OF_LIST="ti/k3-am642-evm ti/k3-am642-sk"
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||
@@ -170,3 +170,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_FUNCTION_MASS_STORAGE=y
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
|
||||
Reference in New Issue
Block a user