arm: mvebu: Add Allied Telesis x960 board
The x960-28YSQ is a 25G/100G layer 3 switch from Allied Telesis. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <stefan.roese@mailbox.org> [sr: fix DT file name in MAINTAINERS]
This commit is contained in:
Chris Packham
committed by
Stefan Roese
Stefan Roese
parent
cd26b17f87
commit
57f382db43
@@ -170,7 +170,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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cn9130-crb-B.dtb \
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ac5-98dx35xx-rd.dtb \
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ac5-98dx35xx-atl-x240.dtb \
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cn9130-atl-x250.dtb
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cn9130-atl-x250.dtb \
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cn9130-atl-x960-28ysq.dtb
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endif
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dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
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@@ -0,0 +1,313 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2026 Allied Telesis Labs
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*/
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#include "cn9130.dtsi"
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/ {
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model = "Allied Telesis x960-28YSQ";
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compatible = "alliedtelesis,x960-28ysq",
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"marvell,cn9130",
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"marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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aliases {
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serial0 = &uart0;
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i2c0 = &cp0_i2c0;
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i2c1 = &cp0_i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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/*
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* AP related configuration
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*/
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&ap_pinctl {
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/* AP_MPP Pins:
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* GPIO & NC [0-10,12]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0 0 0 0 0 0 0 0 0 0
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0 3 0 0 0 0 0 0 0 3 >;
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};
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&ap_gpio0 {
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pp-reset {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "pp-reset";
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};
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usb-en {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-en";
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};
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fan-en {
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gpio-hog;
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gpios = <8 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "fan-en";
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};
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};
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/*
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* CP related configuration
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*/
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&cp0_pinctl {
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/* MPP Bus:
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* [0-1] DEV
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* [2-8] GPIO
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* [9] DEV
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* [10-12] GPIO
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* [13] ND_RB
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* [14] GPIO
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* [15-28] DEV
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* [29-30] GPIO
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* [31] DEV
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* [32-34] GPIO
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* [35-36] I2C1
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* [37-38] I2C0
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* [39-46] GPIO
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* [47] SMI
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* [48] GPIO
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* [49] SMI
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* [49-55] GPIO
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* [56-60] SPI
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* [61-62] GPIO
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 0 0 0 0 0 0 0 1
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0 0 0 2 0 1 1 1 1 1
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1 1 1 1 1 1 1 1 1 0
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0 1 0 0 0 2 2 2 2 0
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0 0 0 0 0 0 0 8 0 8
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0 0 0 0 0 0 6 6 6 6
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6 0 0>;
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = <37 38>;
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marvell,function = <2>;
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = <35 36>;
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marvell,function = <2>;
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};
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cp0_nand_pins: cp0-nand-pins {
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marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>;
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marvell,function = <1>;
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};
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cp0_smi_pins: cp0-smi-pins {
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marvell,pins = <47 49>;
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marvell,function = <8>;
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};
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cp0_nand_rb: cp0-nand-rb {
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marvell,pins = <13>;
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marvell,function = <2>;
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};
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cp0_spi0_pins: cp0-spi-pins-0 {
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marvell,pins = <56 57 58 59 60>;
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marvell,function = <6>;
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};
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};
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&cp0_i2c0 {
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status = "okay";
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&cp0_i2c0_pins>;
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mux@70 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9546";
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reg = <0x70>;
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i2c-mux-idle-disconnect;
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reset-gpios = <&ap_gpio0 2 GPIO_ACTIVE_LOW>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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hwmon@2d {
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compatible = "adi,adt7476";
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reg = <0x2d>;
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adi,pwm-active-state = <0 0 0>;
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};
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hwmon@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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rtc:rtc@68 {
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compatible = "adi,max31343";
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reg = <0x68>;
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};
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};
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/* Switch/EEPROM */
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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/* PSU0 */
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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eeprom@51 {
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compatible = "i2c-eeprom";
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reg = <0x51>;
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};
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};
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/* PSU1 */
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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eeprom@51 {
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compatible = "i2c-eeprom";
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reg = <0x51>;
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};
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};
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};
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};
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&cp0_i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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};
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&cp0_comphy {
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SGMII0>;
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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};
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&cp0_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_smi_pins>;
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status = "okay";
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cp0_phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth2 {
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status = "okay";
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phy = <&cp0_phy0>;
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phy-mode = "sgmii";
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phy-reset-gpios = <&cp0_gpio0 10 GPIO_ACTIVE_LOW>;
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};
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&cp0_pcie0 {
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num-lanes = <1>;
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/* non-prefetchable memory */
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ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
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status = "disabled";
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};
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&uart0 {
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status = "okay";
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};
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&cp0_utmi0 {
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status = "okay";
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};
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&cp0_usb3_0 {
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status = "okay";
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};
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&cp0_spi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi0_pins>;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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};
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};
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&cp0_nand {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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nand-timing-mode = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@user {
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reg = <0x00000000 0x20000000>;
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label = "user";
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};
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};
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};
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&cp0_gpio0
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{
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nand-protect {
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gpio-hog;
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gpios = <29 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "nand-protect";
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};
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};
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@@ -238,6 +238,11 @@ config TARGET_X220
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bool "Support Allied Telesis x220"
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select 98DX3336
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config TARGET_X960
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bool "Support Allied Telesis x960"
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select ARMADA_8K
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imply BOOTSTD_DEFAULTS
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config TARGET_DB_XC3_24G4XG
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bool "Support DB-XC3-24G4XG"
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select 98DX3336
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@@ -323,6 +328,7 @@ config SYS_BOARD
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default "x250" if TARGET_X250
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default "x240" if TARGET_X240
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default "x220" if TARGET_X220
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default "x960" if TARGET_X960
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default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
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default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
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default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
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@@ -349,6 +355,7 @@ config SYS_CONFIG_NAME
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default "x250" if TARGET_X250
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default "x240" if TARGET_X240
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default "x220" if TARGET_X220
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default "x960" if TARGET_X960
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default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
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default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
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default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
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@@ -375,6 +382,7 @@ config SYS_VENDOR
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default "alliedtelesis" if TARGET_X250
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default "alliedtelesis" if TARGET_X240
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default "alliedtelesis" if TARGET_X220
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default "alliedtelesis" if TARGET_X960
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default "mikrotik" if TARGET_CRS3XX_98DX3236
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default "Marvell" if TARGET_MVEBU_ALLEYCAT5
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@@ -0,0 +1,7 @@
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X960 BOARD
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M: Chris Packham <chris.packham@alliedtelesis.co.nz>
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S: Maintained
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F: board/alliedtelesis/x960/
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F: arch/arm/dts/cn9130-atl-x960-28ysq.dts
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F: include/configs/x960.h
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F: configs/x960_defconfig
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@@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2026 Allied Telesis
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#
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obj-y += x960.o
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@@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <config.h>
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#include <asm/global_data.h>
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#include <linux/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define DEVICE_BUS_SYNC_CTRL 0xF27004C8
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int board_init(void)
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{
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
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/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
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writel(0x00004001, DEVICE_BUS_SYNC_CTRL);
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return 0;
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}
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@@ -0,0 +1,104 @@
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CONFIG_ARM=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_TEXT_BASE=0x00000000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
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CONFIG_TARGET_X960=y
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CONFIG_ENV_SIZE=0x10000
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CONFIG_ENV_OFFSET=0xf80000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="cn9130-atl-x960-28ysq"
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CONFIG_SYS_LOAD_ADDR=0x10000000
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CONFIG_DEBUG_UART_BASE=0xf0512000
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CONFIG_DEBUG_UART_CLOCK=200000000
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_FIT=y
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CONFIG_FIT_SIGNATURE=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BOOTCOMMAND="run distro_bootcmd"
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CONFIG_USE_PREBOOT=y
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CONFIG_SPL_SILENT_CONSOLE=y
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CONFIG_TPL_SILENT_CONSOLE=y
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_UBI=y
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CONFIG_MAC_PARTITION=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_ENV_RELOC_GD_ENV_ADDR=y
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CONFIG_ENV_MMC_DEVICE_INDEX=1
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CONFIG_ARP_TIMEOUT=200
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CONFIG_NET_RETRY_COUNT=50
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CONFIG_IPV6=y
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CONFIG_SYS_64BIT_LBA=y
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CONFIG_GPIO_HOG=y
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CONFIG_DM_I2C=y
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CONFIG_DM_I2C_GPIO=y
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CONFIG_SYS_I2C_MVTWSI=y
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CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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# CONFIG_INPUT is not set
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MISC=y
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# CONFIG_MMC is not set
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_USE_FLASH_BBT=y
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CONFIG_NAND_PXA3XX=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SPI_FLASH_SFDP_SUPPORT=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MVPP2=y
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CONFIG_PHY_MARVELL=y
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CONFIG_NVME_PCI=y
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CONFIG_PCIE_DW_MVEBU=y
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CONFIG_PHY=y
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CONFIG_MVEBU_COMPHY_SUPPORT=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_ARMADA_8K=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_DS1307=y
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CONFIG_RTC_MAX313XX=y
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CONFIG_SCSI=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_SYS_NS16550=y
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||||
CONFIG_KIRKWOOD_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
# CONFIG_TOOLS_MKEFICAPSULE is not set
|
||||
@@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2026 Allied Telesis
|
||||
*/
|
||||
|
||||
#ifndef __X960_H_
|
||||
#define __X960_H_
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CFG_SYS_TCLK 250000000 /* 250MHz */
|
||||
|
||||
/* additions for new ARM relocation support */
|
||||
#define CFG_SYS_SDRAM_BASE 0x00000000
|
||||
|
||||
#define BOOT_TARGETS "usb scsi pxe dhcp"
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"scriptaddr=0x6d00000\0" \
|
||||
"pxefile_addr_r=0x6e00000\0" \
|
||||
"fdt_addr_r=0x6f00000\0" \
|
||||
"kernel_addr_r=0x7000000\0" \
|
||||
"ramdisk_addr_r=0xa000000\0" \
|
||||
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"boot_targets=" BOOT_TARGETS "\0"
|
||||
|
||||
#endif /* __X960_H_ */
|
||||
Reference in New Issue
Block a user