vhaudiquet/u-boot-krane
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

imx: Remove hardcoded watchdog base address macros

Browse Source 
The watchdog base addresses are now obtained from the devicetree via
ofnode_* functions. Remove the hardcoded macro definitions as they are
no longer needed.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Alice Guo
2026-06-05 08:58:00 -03:00
committed by Fabio Estevam
parent 3cacd1b180
commit 4f8d6c8f41
16 changed files with 0 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/asm/arch-imx8ulp/imx-regs.h
-2
View File
@@ -20,8 +20,6 @@
#define SIM1_BASE_ADDR 0x29290000
#define WDG3_RBASE 0x292a0000UL
#define SIM_SEC_BASE_ADDR 0x2802B000
#define CGC1_SOSCDIV_ADDR 0x292C0108
arch/arm/include/asm/arch-imx9/imx-regs.h
-9
View File
@@ -17,15 +17,6 @@
#define ANATOP_BASE_ADDR 0x44480000UL
#ifdef CONFIG_IMX94
#define WDG3_BASE_ADDR 0x49220000UL
#define WDG4_BASE_ADDR 0x49230000UL
#else
#define WDG3_BASE_ADDR 0x42490000UL
#define WDG4_BASE_ADDR 0x424a0000UL
#endif
#define WDG5_BASE_ADDR 0x424b0000UL
#define GPIO2_BASE_ADDR 0x43810000UL
#define GPIO3_BASE_ADDR 0x43820000UL
#define GPIO4_BASE_ADDR 0x43840000UL
include/configs/imx8ulp_evk.h
-2
View File
@@ -30,6 +30,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_RBASE
#endif
include/configs/imx91_evk.h
-2
View File
@@ -16,6 +16,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/imx91_frdm.h
-2
View File
@@ -20,6 +20,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/imx93_evk.h
-3
View File
@@ -26,7 +26,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/imx93_frdm.h
-3
View File
@@ -20,7 +20,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/imx93_qsb.h
-2
View File
@@ -16,6 +16,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/imx93_var_som.h
-3
View File
@@ -38,7 +38,4 @@
#define CFG_SYS_FSL_USDHC_NUM 2
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/imx94_evk.h
-3
View File
@@ -18,7 +18,4 @@
#define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */
#define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/imx95_evk.h
-2
View File
@@ -23,6 +23,4 @@
#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB (Totally 16GB) */
#endif
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif
include/configs/kontron-osm-s-mx93.h
-2
View File
@@ -25,6 +25,4 @@
#define CFG_MXC_USB_FLAGS 0
#endif
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif /* __KONTRON_MX93_CONFIG_H */
include/configs/mx7ulp_com.h
-3
View File
@@ -15,9 +15,6 @@
#include "imx7ulp_spl.h"
#endif
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
/* UART */
include/configs/mx7ulp_evk.h
-3
View File
@@ -11,9 +11,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
/* UART */
include/configs/phycore_imx91_93.h
-3
View File
@@ -22,7 +22,4 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif /* __PHYCORE_IMX91_93_H */
include/configs/toradex-smarc-imx95.h
-2
View File
@@ -19,6 +19,4 @@
#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M)
#define PHYS_SDRAM_2_SIZE SZ_6G
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif