Merge patch series "Print Reset Reason for K3 based devices"

Wadim Egorov <w.egorov@phytec.de> says:

Although AM62x, AM62Ax, AM64x, and AM62Px share the same register for
reset reason, not all TRMs document this consistently. To avoid relying
on undocumented behavior, introduce SoC-specific implementations for
now. If TI confirms all SoCs share the same register, this can be moved to
common.c for reuse.

It will be mostly copy&paste for the mentioned devices.

Also, I am not sure how this Register operates exactly. I noticed that
two bits can be set at once, so I started to check for set bits instead
of having a switch/case logic.

Link: https://lore.kernel.org/r/20250515111554.2916254-1-w.egorov@phytec.de

arch/arm/mach-k3/am62x/boot.c

@@ -101,3 +101,43 @@ u32 get_boot_device(void)
 
 	return bootmedia;
 }
+
+const char *get_reset_reason(void)
+{
+	u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC);
+
+	/* After reading reset source register, software must clear it */
+	if (reset_reason)
+		writel(reset_reason, CTRLMMR_MCU_RST_SRC);
+
+	if (reset_reason == 0 ||
+	   (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN |
+			    RST_SRC_SW_MAIN_POR_FROM_MCU |
+			    RST_SRC_DS_MAIN_PORZ)))
+		return "POR";
+
+	if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR))
+		return "ESM";
+
+	if (reset_reason & RST_SRC_DM_WDT_RST)
+		return "WDOG";
+
+	if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN |
+			    RST_SRC_SW_MAIN_WARM_FROM_MCU  |
+			    RST_SRC_SW_MCU_WARM_RST))
+		return "RST";
+
+	if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST))
+		return "DMSC";
+
+	if (reset_reason & RST_SRC_DEBUG_RST)
+		return "JTAG";
+
+	if (reset_reason & RST_SRC_THERMAL_RST)
+		return "THERMAL";
+
+	if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN))
+		return "PIN";
+
+	return "UNKNOWN";
+}

arch/arm/mach-k3/common.c

@@ -175,11 +175,17 @@ static const char *get_device_type_name(void)
 	}
 }
 
+__weak const char *get_reset_reason(void)
+{
+	return NULL;
+}
+
 int print_cpuinfo(void)
 {
 	struct udevice *soc;
 	char name[64];
 	int ret;
+	const char *reset_reason;
 
 	printf("SoC:   ");
 
@@ -201,6 +207,10 @@ int print_cpuinfo(void)
 
 	printf("%s\n", get_device_type_name());
 
+	reset_reason = get_reset_reason();
+	if (reset_reason)
+		printf("Reset reason: %s\n", reset_reason);
+
 	return 0;
 }
 #endif

arch/arm/mach-k3/include/mach/am62_hardware.h

@@ -79,6 +79,25 @@
 
 #define CTRLMMR_MCU_RST_CTRL			(MCU_CTRL_MMR0_BASE + 0x18170)
 
+/* Reset Reason Detection */
+#define CTRLMMR_MCU_RST_SRC			(MCU_CTRL_MMR0_BASE + 0x18178)
+
+#define RST_SRC_SAFETY_ERR			BIT(31)
+#define RST_SRC_MAIN_ESM_ERR			BIT(30)
+#define RST_SRC_SW_MAIN_POR_FROM_MAIN		BIT(25)
+#define RST_SRC_SW_MAIN_POR_FROM_MCU		BIT(24)
+#define RST_SRC_DS_MAIN_PORZ			BIT(23)
+#define RST_SRC_DM_WDT_RST			BIT(22)
+#define RST_SRC_SW_MAIN_WARM_FROM_MAIN		BIT(21)
+#define RST_SRC_SW_MAIN_WARM_FROM_MCU		BIT(20)
+#define RST_SRC_SW_MCU_WARM_RST			BIT(16)
+#define RST_SRC_SMS_WARM_RST			BIT(13)
+#define RST_SRC_SMS_COLD_RST			BIT(12)
+#define RST_SRC_DEBUG_RST			BIT(8)
+#define RST_SRC_THERMAL_RST			BIT(4)
+#define RST_SRC_MAIN_RESET_PIN			BIT(2)
+#define RST_SRC_MCU_RESET_PIN			BIT(0)
+
 /* Debounce register configuration */
 #define CTRLMMR_DBOUNCE_CFG(index)		(MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4))
 

arch/arm/mach-k3/include/mach/hardware.h

@@ -125,4 +125,5 @@ struct rom_extended_boot_data {
 };
 
 u32 get_boot_device(void);
+const char *get_reset_reason(void);
 #endif /* _ASM_ARCH_HARDWARE_H_ */