clk: sunxi: Add MBUS Master Clock Gating Register

Add MBUS Master Clock Gating Register for H6 and H616

For H6/H616, the NAND controller needs the MBUS NAND clock along with
CLK_NAND0/1 and CLK_BUS_NAND.

The bit locations are from H6/H616 User Manuals.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

drivers/clk/sunxi/clk_h6.c

@@ -20,6 +20,8 @@ static struct ccu_clk_gate h6_gates[] = {
 	[CLK_DE]		= GATE(0x600, BIT(31)),
 	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
 
+	[CLK_MBUS_NAND]		= GATE(0x804, BIT(5)),
+
 	[CLK_NAND0]		= GATE(0x810, BIT(31)),
 	[CLK_NAND1]		= GATE(0x814, BIT(31)),
 	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),

drivers/clk/sunxi/clk_h616.c

@@ -19,6 +19,8 @@ static struct ccu_clk_gate h616_gates[] = {
 	[CLK_DE]		= GATE(0x600, BIT(31)),
 	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
 
+	[CLK_MBUS_NAND]		= GATE(0x804, BIT(5)),
+
 	[CLK_NAND0]		= GATE(0x810, BIT(31)),
 	[CLK_NAND1]		= GATE(0x814, BIT(31)),
 	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),