pinctrl: imx: Split imx_pinctrl_set_state() into common and mmio parts

Split imx_pinctrl_set_state() into imx_pinctrl_set_state_common() and
imx_pinctrl_set_state_mmio(). The former does the common configuration
parsing, the later does call imx_pinctrl_set_state_common() and then
does pin configuration using either SCU or MMIO accesses. The SCU part
is going to be moved out in follow up patches.

This is a preparatory patch for follow up pinctrl drivers which
do not use the MMIO accessors, but some other means, like SCU or
otherwise. Those will call the common imx_pinctrl_set_state_common()
function wrapped into some other imx_pinctrl_set_state_*() function,
in a way similar to imx_pinctrl_set_state_mmio() does so for MMIO
accesses.

Update all imx_pinctrl_set_state_mmio() call sites to call
imx_pinctrl_set_state_mmio() instead.

No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>

drivers/pinctrl/nxp/pinctrl-imx.c

@@ -18,28 +18,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config,
+				 int pin_size, u32 **pin_data, int *npins)
 {
-	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
-	struct imx_pinctrl_soc_info *info = priv->info;
 	ofnode node = dev_ofnode(config);
 	const struct fdt_property *prop;
-	u32 *pin_data;
-	int npins, size, pin_size;
-	int mux_reg, conf_reg, input_reg;
-	u32 input_val, mux_mode, config_val;
-	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
-	int i, j = 0;
+	int size;
 
 	dev_dbg(dev, "%s: %s\n", __func__, config->name);
 
-	if (info->flags & IMX8_USE_SCU)
-		pin_size = SHARE_IMX8_PIN_SIZE;
-	else if (info->flags & SHARE_MUX_CONF_REG)
-		pin_size = SHARE_FSL_PIN_SIZE;
-	else
-		pin_size = FSL_PIN_SIZE;
-
 	prop = ofnode_get_property(node, "fsl,pins", &size);
 	if (!prop) {
 		dev_err(dev, "No fsl,pins property in node %s\n", config->name);
@@ -52,18 +39,43 @@ int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 		return -EINVAL;
 	}
 
-	pin_data = devm_kzalloc(dev, size, 0);
-	if (!pin_data)
+	*pin_data = devm_kzalloc(dev, size, 0);
+	if (!*pin_data)
 		return -ENOMEM;
 
-	if (ofnode_read_u32_array(node, "fsl,pins",
-				  pin_data, size >> 2)) {
+	if (ofnode_read_u32_array(node, "fsl,pins", *pin_data, size >> 2)) {
 		dev_err(dev, "Error reading pin data.\n");
-		devm_kfree(dev, pin_data);
+		devm_kfree(dev, *pin_data);
 		return -EINVAL;
 	}
 
-	npins = size / pin_size;
+	*npins = size / pin_size;
+
+	return 0;
+}
+
+int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config)
+{
+	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+	struct imx_pinctrl_soc_info *info = priv->info;
+	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
+	u32 input_val, mux_mode, config_val;
+	int mux_reg, conf_reg, input_reg;
+	int npins, pin_size;
+	int i, j = 0, ret;
+	u32 *pin_data;
+
+	if (info->flags & IMX8_USE_SCU)
+		pin_size = SHARE_IMX8_PIN_SIZE;
+	else if (info->flags & SHARE_MUX_CONF_REG)
+		pin_size = SHARE_FSL_PIN_SIZE;
+	else
+		pin_size = FSL_PIN_SIZE;
+
+	ret = imx_pinctrl_set_state_common(dev, config, pin_size,
+					   &pin_data, &npins);
+	if (ret)
+		return ret;
 
 	if (info->flags & IMX8_USE_SCU) {
 		imx_pinctrl_scu_conf_pins(info, pin_data, npins);

drivers/pinctrl/nxp/pinctrl-imx.h

@@ -53,7 +53,9 @@ int imx_pinctrl_probe_mmio(struct udevice *dev);
 
 int imx_pinctrl_remove_mmio(struct udevice *dev);
 
-int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config);
+int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config,
+				 int pin_size, u32 **pin_data, int *npins);
+int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config);
 
 #ifdef CONFIG_PINCTRL_IMX_SCU
 int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,

drivers/pinctrl/nxp/pinctrl-imx5.c

@@ -24,7 +24,7 @@ static const struct udevice_id imx5_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx5_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imx5_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-imx6.c

@@ -33,7 +33,7 @@ static const struct udevice_id imx6_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx6_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(fsl_imx6q_iomuxc) = {

drivers/pinctrl/nxp/pinctrl-imx7.c

@@ -21,7 +21,7 @@ static const struct udevice_id imx7_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx7_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imx7_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-imx7ulp.c

@@ -25,7 +25,7 @@ static const struct udevice_id imx7ulp_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx7ulp_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imx7ulp_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-imx8.c

@@ -22,7 +22,7 @@ static const struct udevice_id imx8_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx8_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imx8_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-imx8m.c

@@ -19,7 +19,7 @@ static const struct udevice_id imx8m_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx8m_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imx8mq_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-imx8ulp.c

@@ -24,7 +24,7 @@ static const struct udevice_id imx8ulp_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx8ulp_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imx8ulp_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-imx93.c

@@ -19,7 +19,7 @@ static const struct udevice_id imx93_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imx93_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imx93_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-imxrt.c

@@ -20,7 +20,7 @@ static const struct udevice_id imxrt_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops imxrt_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(imxrt_pinctrl) = {

drivers/pinctrl/nxp/pinctrl-vf610.c

@@ -20,7 +20,7 @@ static const struct udevice_id vf610_pinctrl_match[] = {
 };
 
 static const struct pinctrl_ops vf610_pinctrl_ops = {
-	.set_state = imx_pinctrl_set_state,
+	.set_state = imx_pinctrl_set_state_mmio,
 };
 
 U_BOOT_DRIVER(vf610_pinctrl) = {