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riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next

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Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream
"riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
E Shattow
2025-09-19 19:23:32 +08:00
committed by Leo Yu-Chi Liang
parent 27f617019d
commit 3e6d5b205d
1 changed files with 32 additions and 51 deletions
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arch/riscv/dts/jh7110-u-boot.dtsi
+32 -51
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@@ -3,37 +3,11 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
#include <dt-bindings/reset/starfive,jh7110-crg.h>
/ {
timer {
compatible = "riscv,timer";
interrupts-extended = <&cpu0_intc 5>,
<&cpu1_intc 5>,
<&cpu2_intc 5>,
<&cpu3_intc 5>,
<&cpu4_intc 5>;
};
soc {
bootph-pre-ram;
dmc: dmc@15700000 {
bootph-pre-ram;
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll1_out";
clock-frequency = <2133>;
};
};
};
&clint {
bootph-pre-ram;
};
@@ -58,22 +32,10 @@
bootph-pre-ram;
};
&cpus {
bootph-pre-ram;
};
&osc {
bootph-pre-ram;
};
&gmac0_rgmii_rxin {
bootph-pre-ram;
};
&gmac0_rmii_refin {
bootph-pre-ram;
};
&gmac1_rgmii_rxin {
bootph-pre-ram;
};
@@ -82,7 +44,24 @@
bootph-pre-ram;
};
&aoncrg {
/ {
soc {
memory-controller@15700000 {
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
bootph-pre-ram;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
};
};
};
&syscrg {
bootph-pre-ram;
};
@@ -90,15 +69,17 @@
bootph-pre-ram;
};
// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
/ {
soc {
memory-controller@15700000 {
clock-frequency = <2133>; /* FIXME: delete property and implement CCF */
};
};
};
&syscrg {
assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
bootph-pre-ram;
assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */
};
&stgcrg {
bootph-pre-ram;
};
&sys_syscon {
bootph-pre-ram;
};