arm: npcm8xx: add security feature header
The NPCM driver can use on npcm7xx/npcm8xx so add npcm8xx header for driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
Tom Rini
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_AES_H_
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#define _NPCM_AES_H_
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#define AES_OP_ENCRYPT 0
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#define AES_OP_DECRYPT 1
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#define SIZE_AES_BLOCK (AES128_KEY_LENGTH)
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struct npcm_aes_regs {
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unsigned char reserved_0[0x400]; // 0x000
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unsigned int aes_key_0; // 0x400
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unsigned int aes_key_1; // 0x404
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unsigned int aes_key_2; // 0x408
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unsigned int aes_key_3; // 0x40c
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unsigned char reserved_1[0x30]; // 0x410
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unsigned int aes_iv_0; // 0x440
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unsigned char reserved_2[0x1c]; // 0x444
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unsigned int aes_ctr_0; // 0x460
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unsigned char reserved_3[0x0c]; // 0x464
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unsigned int aes_busy; // 0x470
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unsigned char reserved_4[0x04]; // 0x474
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unsigned int aes_sk; // 0x478
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unsigned char reserved_5[0x14]; // 0x47c
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unsigned int aes_prev_iv_0; // 0x490
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unsigned char reserved_6[0x0c]; // 0x494
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unsigned int aes_din_dout; // 0x4a0
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unsigned char reserved_7[0x1c]; // 0x4a4
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unsigned int aes_control; // 0x4c0
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unsigned int aes_version; // 0x4c4
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unsigned int aes_hw_flags; // 0x4c8
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unsigned char reserved_8[0x28]; // 0x4cc
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unsigned int aes_sw_reset; // 0x4f4
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unsigned char reserved_9[0x08]; // 0x4f8
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unsigned int aes_fifo_data; // 0x500
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unsigned char reserved_10[0xfc]; // 0x504
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unsigned int aes_fifo_status; // 0x600
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};
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#define AES_BUSY_BIT BIT(0)
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#define SW_RESET_BIT BIT(0)
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#define AES_SK_BIT BIT(0)
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#define DIN_FIFO_FULL BIT(0)
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#define DIN_FIFO_EMPTY BIT(1)
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#define DOUT_FIFO_FULL BIT(2)
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#define DOUT_FIFO_EMPTY BIT(3)
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#define DIN_FIFO_OVERFLOW BIT(4)
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#define DOUT_FIFO_UNDERFLOW BIT(5)
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int npcm_aes_select_key(u8 fkeyind);
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#endif
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@@ -0,0 +1,93 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_OTP_H_
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#define _NPCM_OTP_H_
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#ifdef CONFIG_ARCH_NPCM8XX
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enum {
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NPCM_KEY_SA = 0,
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NPCM_FUSE_SA = 0,
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NPCM_NUM_OF_SA = 1
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};
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#else
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enum {
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NPCM_KEY_SA = 0,
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NPCM_FUSE_SA = 1,
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NPCM_NUM_OF_SA = 2
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};
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#endif
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/* arrray images in flash, to program during fisrt boot (offsets in sector) */
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#define SA_KEYS_FLASH_IMAGE_OFFSET (0x000)
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#define SA_FUSE_FLASH_IMAGE_OFFSET (0x400)
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#define SA_TAG_FLASH_IMAGE_OFFSET (0x800)
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/* F U S E I M G S */
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#define SA_TAG_FLASH_IMAGE_VAL {0x46, 0x55, 0x53, 0x45, 0x49, 0x4d, 0x47, 0x53}
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#define SA_TAG_FLASH_IMAGE_SIZE (8)
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#define SA_FUSE_FUSTRAP_OFFSET (0x00)
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#define SA_FUSE_FUSTRAP_OSECBOOT_MASK (0x00800000)
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struct npcm_otp_regs {
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unsigned int fst;
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unsigned int faddr;
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unsigned int fdata;
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unsigned int fcfg;
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unsigned int fustrap_fkeyind;
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unsigned int fctl;
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};
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#define FST_RDY BIT(0)
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#define FST_RDST BIT(1)
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#define FST_RIEN BIT(2)
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#ifdef CONFIG_ARCH_NPCM8XX
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#define FADDR_BYTEADDR(addr) ((addr) << 3)
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#define FADDR_BITPOS(pos) ((pos) << 0)
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#define FADDR_VAL(addr, pos) (FADDR_BITPOS(pos) | FADDR_BYTEADDR(addr))
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#define FADDR_IN_PROG BIT(16)
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#else
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#define FADDR_BYTEADDR(addr) ((addr) << 0)
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#define FADDR_BITPOS(pos) ((pos) << 10)
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#define FADDR_VAL(addr, pos) (FADDR_BYTEADDR(addr) | FADDR_BITPOS(pos))
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#endif
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#define FDATA_MASK (0xff)
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#define FUSTRAP_O_SECBOOT BIT(23)
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#define FCFG_FDIS BIT(31)
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#define FKEYIND_KVAL BIT(0)
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#define FKEYIND_KSIZE_MASK (0x00000070)
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#define FKEYIND_KSIZE_128 (0x4 << 4)
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#define FKEYIND_KSIZE_192 (0x5 << 4)
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#define FKEYIND_KSIZE_256 (0x6 << 4)
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#define FKEYIND_KIND_MASK (0x000c0000)
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#define FKEYIND_KIND_KEY(indx) ((indx) << 18)
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/* Program cycle initiation values (sequence of two adjacent writes) */
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#define PROGRAM_ARM 0x1
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#define PROGRAM_INIT 0xBF79E5D0
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/* Read cycle initiation value */
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#define READ_INIT 0x02
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/* Value to clean FDATA contents */
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#define FDATA_CLEAN_VALUE 0x01
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#ifdef CONFIG_ARCH_NPCM8XX
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#define NPCM_OTP_ARR_BYTE_SIZE 8192
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#else
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#define NPCM_OTP_ARR_BYTE_SIZE 1024
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#endif
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#define MIN_PROGRAM_PULSES 4
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#define MAX_PROGRAM_PULSES 20
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int fuse_prog_image(u32 bank, uintptr_t address);
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int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size);
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int npcm_otp_select_key(u8 key_index);
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bool npcm_otp_is_fuse_array_disabled(u32 arr);
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void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size);
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void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size);
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#endif
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@@ -0,0 +1,43 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_RNG_H_
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#define _NPCM_RNG_H_
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struct npcm_rng_regs {
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unsigned int rngcs;
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unsigned int rngd;
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unsigned int rngmode;
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};
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#define RNGCS_RNGE (1 << 0)
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#define RNGCS_DVALID (1 << 1)
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#define RNGCS_CLKP(range) ((0x0f & (range)) << 2)
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#define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I */
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/*----------------------------------------------------------------------------*/
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/* Core Domain Clock Frequency Range for the selected value is higher */
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/* than or equal to the actual Core domain clock frequency */
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/*----------------------------------------------------------------------------*/
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enum {
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RNG_CLKP_80_100_MHZ = 0x00, /*default */
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RNG_CLKP_60_80_MHZ = 0x01,
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RNG_CLKP_50_60_MHZ = 0x02,
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RNG_CLKP_40_50_MHZ = 0x03,
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RNG_CLKP_30_40_MHZ = 0x04,
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RNG_CLKP_25_30_MHZ = 0x05,
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RNG_CLKP_20_25_MHZ = 0x06,
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RNG_CLKP_5_20_MHZ = 0x07,
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RNG_CLKP_2_15_MHZ = 0x08,
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RNG_CLKP_9_12_MHZ = 0x09,
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RNG_CLKP_7_9_MHZ = 0x0A,
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RNG_CLKP_6_7_MHZ = 0x0B,
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RNG_CLKP_5_6_MHZ = 0x0C,
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RNG_CLKP_4_5_MHZ = 0x0D,
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RNG_CLKP_3_4_MHZ = 0x0E,
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RNG_NUM_OF_CLKP
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};
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void npcm_rng_init(void);
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void npcm_rng_disable(void);
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#endif
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@@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_SHA_H_
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#define _NPCM_SHA_H_
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#define HASH_DIG_H_NUM 8
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/* SHA type */
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enum npcm_sha_type {
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npcm_sha_type_sha2 = 0,
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npcm_sha_type_sha1,
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npcm_sha_type_num
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};
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struct npcm_sha_regs {
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unsigned int hash_data_in;
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unsigned char hash_ctr_sts;
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unsigned char reserved_0[0x03];
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unsigned char hash_cfg;
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unsigned char reserved_1[0x03];
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unsigned char hash_ver;
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unsigned char reserved_2[0x13];
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unsigned int hash_dig[HASH_DIG_H_NUM];
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};
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#define HASH_CTR_STS_SHA_EN BIT(0)
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#define HASH_CTR_STS_SHA_BUSY BIT(1)
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#define HASH_CTR_STS_SHA_RST BIT(2)
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#define HASH_CFG_SHA1_SHA2 BIT(0)
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int npcm_sha_calc(u8 type, const u8 *buf, u32 len, u8 *digest);
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int npcm_sha_selftest(u8 type);
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#endif
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