The highlights are: * Fixed boot regression due to broken memory parsing * Enable HW RNG and KASLR on all platforms * Add support for Snapdragon X1 Elite hardware (clk/pinctrl) * Add support for QCS9100 ride automotive development platform (clk/ufs) * Add support for PCIe on SM8550, SM8650 and X1E * Implement software debounce for PMIC buttons Additionally, some minor improvements to "ufetch" have been pulled in: * Show CPU architecture (arm/mips/etc) * Make CONFIG_BLK optional * Fix 32-bit support
This commit is contained in:
Tom Rini
@@ -631,6 +631,7 @@ L: u-boot-qcom@groups.io
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S: Maintained
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T: git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git
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F: configs/qcm6490_defconfig
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F: configs/qcs9100_defconfig
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F: drivers/*/*/pm8???-*
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F: drivers/gpio/msm_gpio.c
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F: drivers/mmc/msm_sdhci.c
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@@ -0,0 +1,20 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/ {
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/* Will be removed when bootloader updates later */
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x3ee00000>,
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<0x0 0xc0000000 0x0 0x04d00000>,
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<0xd 0x00000000 0x2 0x54100000>,
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<0xa 0x80000000 0x1 0x52d00000>,
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<0x9 0x00000000 0x1 0x80000000>,
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<0x1 0x00000000 0x2 0xf7500000>,
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<0x0 0xd0000000 0x0 0x00100000>,
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<0x0 0xd3500000 0x0 0x07c00000>,
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<0x0 0xdb300000 0x0 0x24d00000>;
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};
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};
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@@ -88,20 +88,21 @@ int dram_init_banksize(void)
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return 0;
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}
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static void qcom_parse_memory(void)
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static void qcom_parse_memory(const void *fdt)
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{
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ofnode node;
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int offset;
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const fdt64_t *memory;
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int memsize;
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phys_addr_t ram_end = 0;
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int i, j, banks;
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node = ofnode_path("/memory");
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if (!ofnode_valid(node)) {
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offset = fdt_path_offset(fdt, "/memory");
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if (offset < 0) {
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log_err("No memory node found in device tree!\n");
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return;
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}
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memory = ofnode_read_prop(node, "reg", &memsize);
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memory = fdt_getprop(fdt, offset, "reg", &memsize);
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if (!memory) {
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log_err("No memory configuration was provided by the previous bootloader!\n");
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return;
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@@ -158,7 +159,7 @@ int board_fdt_blob_setup(void **fdtp)
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fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
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external_valid = fdt && !fdt_check_header(fdt);
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internal_valid = !fdt_check_header(gd->fdt_blob);
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internal_valid = !fdt_check_header(*fdtp);
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/*
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* There is no point returning an error here, U-Boot can't do anything useful in this situation.
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@@ -181,7 +182,7 @@ int board_fdt_blob_setup(void **fdtp)
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* Parse the /memory node while we're here,
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* this makes it easy to do other things early.
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*/
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qcom_parse_memory();
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qcom_parse_memory(*fdtp);
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return ret;
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}
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@@ -178,7 +178,6 @@ config CMD_CPU
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config CMD_UFETCH
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bool "U-Boot fetch"
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depends on BLK
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help
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Fetch utility for U-Boot (akin to neofetch). Prints information
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about U-Boot and the board it is running on in a pleasing format.
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+11
-6
@@ -89,14 +89,12 @@ enum output_lines {
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static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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int num_lines = max(LAST_LINE + 1, ARRAY_SIZE(logo_lines));
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int num_lines = max((size_t)LAST_LINE + 1, ARRAY_SIZE(logo_lines));
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const char *model, *compatible;
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char *ipaddr;
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int n_cmds, n_cpus = 0, ret, compatlen;
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int n_cmds, n_cpus = 0, compatlen;
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size_t size;
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ofnode np;
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struct udevice *dev;
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struct blk_desc *desc;
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bool skip_ascii = false;
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if (argc > 1 && strcmp(argv[1], "-n") == 0) {
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@@ -190,7 +188,7 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
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if (ofnode_name_eq(np, "cpu"))
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n_cpus++;
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}
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printf("CPU:" RESET " %d (1 in use)\n", n_cpus);
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printf("CPU: " RESET CONFIG_SYS_ARCH " (%d cores, 1 in use)\n", n_cpus);
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break;
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case MEMORY:
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for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++)
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@@ -199,7 +197,12 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
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print_size(size, "\n");
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break;
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case STORAGE:
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default:
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default: {
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#ifdef CONFIG_BLK
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struct udevice *dev;
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struct blk_desc *desc;
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int ret;
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ret = uclass_find_device_by_seq(UCLASS_BLK, line - STORAGE, &dev);
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if (!ret && dev) {
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desc = dev_get_uclass_plat(dev);
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@@ -213,8 +216,10 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
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} else if (ret == -ENODEV && (skip_ascii || line > ARRAY_SIZE(logo_lines))) {
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break;
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}
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#endif
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printf("\n");
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}
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}
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}
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printf(RESET "\n\n");
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@@ -37,6 +37,7 @@ CONFIG_CMD_USB=y
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CONFIG_CMD_CAT=y
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CONFIG_CMD_BMP=y
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CONFIG_CMD_EFIDEBUG=y
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CONFIG_CMD_RNG=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_LOG=y
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CONFIG_OF_LIVE=y
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@@ -48,12 +49,14 @@ CONFIG_CLK_QCOM_APQ8016=y
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CONFIG_CLK_QCOM_APQ8096=y
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CONFIG_CLK_QCOM_QCM2290=y
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CONFIG_CLK_QCOM_QCS404=y
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CONFIG_CLK_QCOM_SA8775P=y
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CONFIG_CLK_QCOM_SDM845=y
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CONFIG_CLK_QCOM_SM6115=y
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CONFIG_CLK_QCOM_SM8150=y
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CONFIG_CLK_QCOM_SM8250=y
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CONFIG_CLK_QCOM_SM8550=y
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CONFIG_CLK_QCOM_SM8650=y
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CONFIG_CLK_QCOM_X1E80100=y
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CONFIG_CLK_QCOM_SC7280=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_SCSI=y
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@@ -99,11 +102,14 @@ CONFIG_PINCTRL_QCOM_SM8150=y
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CONFIG_PINCTRL_QCOM_SM8250=y
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CONFIG_PINCTRL_QCOM_SM8550=y
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CONFIG_PINCTRL_QCOM_SM8650=y
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CONFIG_PINCTRL_QCOM_X1E80100=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_QCOM=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_QCOM_RPMH=y
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CONFIG_DM_RNG=y
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CONFIG_RNG_MSM=y
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CONFIG_SCSI=y
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CONFIG_MSM_SERIAL=y
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CONFIG_MSM_GENI_SERIAL=y
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@@ -0,0 +1,18 @@
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# Configuration for building U-Boot to be flashed
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# to the uefi partition of QCS9100 based dev boards with
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# the "Linux Embedded" partition layout (which have
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# a dedicated "uefi" partition for edk2/U-Boot)
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#include "qcom_defconfig"
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_DEBUG_UART_BASE=0xA8C000
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CONFIG_DEBUG_UART_MSM_GENI=y
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CONFIG_DEBUG_UART_CLOCK=14745600
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# Address where U-Boot will be loaded
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CONFIG_TEXT_BASE=0xaf000000
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CONFIG_REMAKE_ELF=y
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CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs9100-ride-r3"
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@@ -15,6 +15,7 @@
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#include <power/pmic.h>
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#include <spmi/spmi.h>
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#include <linux/bitops.h>
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#include <time.h>
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#define REG_TYPE 0x4
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#define REG_SUBTYPE 0x5
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@@ -31,6 +32,7 @@ struct qcom_pmic_btn_priv {
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u32 status_bit;
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int code;
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struct udevice *pmic;
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ulong last_release_time;
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};
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#define PON_INT_RT_STS 0x10
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@@ -42,13 +44,21 @@ struct qcom_pmic_btn_priv {
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static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev)
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{
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struct qcom_pmic_btn_priv *priv = dev_get_priv(dev);
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bool pressed;
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int reg;
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int reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS);
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if (get_timer_us(0) - priv->last_release_time < 25000)
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return BUTTON_OFF;
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reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS);
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if (reg < 0)
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return 0;
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return (reg & BIT(priv->status_bit)) != 0;
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pressed = !!(reg & BIT(priv->status_bit));
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if (!pressed)
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priv->last_release_time = get_timer_us(0);
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return pressed;
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}
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static int qcom_pwrkey_get_code(struct udevice *dev)
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@@ -47,6 +47,14 @@ config CLK_QCOM_QCS404
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on the Snapdragon QCS404 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_SA8775P
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bool "Qualcomm SA8775 GCC"
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select CLK_QCOM
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help
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Say Y here to enable support for the Global Clock Controller
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on the Snapdragon SA8775 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_SDM845
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bool "Qualcomm SDM845 GCC"
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select CLK_QCOM
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@@ -103,6 +111,14 @@ config CLK_QCOM_SC7280
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on the Snapdragon SC7280 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_X1E80100
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bool "Qualcomm X1E80100 GCC"
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select CLK_QCOM
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help
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Say Y here to enable support for the Global Clock Controller
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on the Snapdragon X1E80100 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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endmenu
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endif
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@@ -9,9 +9,11 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
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obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
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obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
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obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
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obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
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obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
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obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
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obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
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obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o
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obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
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obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o
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obj-$(CONFIG_CLK_QCOM_X1E80100) += clock-x1e80100.o
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@@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
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clk_bcr_update(base + cmd_rcgr);
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}
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#define PHY_MUX_MASK GENMASK(1, 0)
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#define PHY_MUX_PHY_SRC 0
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#define PHY_MUX_REF_SRC 2
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void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled)
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{
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u32 cfg;
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/* setup src select and divider */
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cfg = readl(base + cmd_rcgr);
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cfg &= ~(PHY_MUX_MASK);
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if (enabled)
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||||
cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC);
|
||||
else
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cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC);
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||||
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writel(cfg, base + cmd_rcgr);
|
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}
|
||||
|
||||
const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
|
||||
{
|
||||
if (!f)
|
||||
|
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@@ -6,6 +6,7 @@
|
||||
#define _CLOCK_QCOM_H
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#define CFG_CLK_SRC_CXO (0 << 8)
|
||||
#define CFG_CLK_SRC_GPLL0 (1 << 8)
|
||||
@@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
|
||||
int div, int m, int n, int source, u8 mnd_width);
|
||||
void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
|
||||
int source);
|
||||
void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
|
||||
|
||||
static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
|
||||
{
|
||||
|
||||
@@ -0,0 +1,142 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Clock drivers for Qualcomm sa8775p
|
||||
*
|
||||
* (C) Copyright 2024 Linaro Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
#include "clock-qcom.h"
|
||||
|
||||
#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
|
||||
#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
|
||||
|
||||
static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
if (clk->id < priv->data->num_clks)
|
||||
debug("%s: %s, requested rate=%ld\n", __func__,
|
||||
priv->data->clks[clk->id].name, rate);
|
||||
|
||||
switch (clk->id) {
|
||||
case GCC_USB30_PRIM_MOCK_UTMI_CLK:
|
||||
WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
|
||||
clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
|
||||
return rate;
|
||||
case GCC_USB30_PRIM_MASTER_CLK:
|
||||
WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
|
||||
1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
|
||||
clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
|
||||
return rate;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct gate_clk sa8775p_clks[] = {
|
||||
GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1),
|
||||
GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1),
|
||||
GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1),
|
||||
GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1),
|
||||
GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
|
||||
GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
|
||||
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
|
||||
};
|
||||
|
||||
static int sa8775p_enable(struct clk *clk)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
if (priv->data->num_clks < clk->id) {
|
||||
debug("%s: unknown clk id %lu\n", __func__, clk->id);
|
||||
return 0;
|
||||
}
|
||||
|
||||
debug("%s: clk %ld: %s\n", __func__, clk->id, sa8775p_clks[clk->id].name);
|
||||
|
||||
switch (clk->id) {
|
||||
case GCC_AGGRE_USB3_PRIM_AXI_CLK:
|
||||
qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
|
||||
fallthrough;
|
||||
case GCC_USB30_PRIM_MASTER_CLK:
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
|
||||
break;
|
||||
}
|
||||
|
||||
qcom_gate_clk_en(priv, clk->id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct qcom_reset_map sa8775p_gcc_resets[] = {
|
||||
[GCC_CAMERA_BCR] = { 0x32000 },
|
||||
[GCC_DISPLAY1_BCR] = { 0xC7000 },
|
||||
[GCC_DISPLAY_BCR] = { 0x33000 },
|
||||
[GCC_EMAC0_BCR] = { 0xB6000 },
|
||||
[GCC_EMAC1_BCR] = { 0xB4000 },
|
||||
[GCC_GPU_BCR] = { 0x7D000 },
|
||||
[GCC_MMSS_BCR] = { 0x17000 },
|
||||
[GCC_PCIE_0_BCR] = { 0xa9000 },
|
||||
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xBF000 },
|
||||
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xBF008 },
|
||||
[GCC_PCIE_0_PHY_BCR] = { 0xAD144 },
|
||||
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xBF00C },
|
||||
[GCC_PCIE_1_BCR] = { 0x77000 },
|
||||
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0xAE084 },
|
||||
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xAE090 },
|
||||
[GCC_PCIE_1_PHY_BCR] = { 0xAE08C },
|
||||
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xAE094 },
|
||||
[GCC_PDM_BCR] = { 0x3F000 },
|
||||
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
|
||||
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
|
||||
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x2A000 },
|
||||
[GCC_QUPV3_WRAPPER_3_BCR] = { 0xC4000 },
|
||||
[GCC_SDCC1_BCR] = { 0x20000 },
|
||||
[GCC_TSCSS_BCR] = { 0x21000 },
|
||||
[GCC_UFS_CARD_BCR] = { 0x81000 },
|
||||
[GCC_UFS_PHY_BCR] = { 0x83000 },
|
||||
};
|
||||
|
||||
static const struct qcom_power_map sa8775p_gdscs[] = {
|
||||
[UFS_PHY_GDSC] = { 0x83004 },
|
||||
[USB30_PRIM_GDSC] = { 0x1B004 },
|
||||
};
|
||||
|
||||
static struct msm_clk_data sa8775_gcc_data = {
|
||||
.resets = sa8775p_gcc_resets,
|
||||
.num_resets = ARRAY_SIZE(sa8775p_gcc_resets),
|
||||
.clks = sa8775p_clks,
|
||||
.num_clks = ARRAY_SIZE(sa8775p_clks),
|
||||
|
||||
.power_domains = sa8775p_gdscs,
|
||||
.num_power_domains = ARRAY_SIZE(sa8775p_gdscs),
|
||||
|
||||
.enable = sa8775p_enable,
|
||||
.set_rate = sa8775p_set_rate,
|
||||
};
|
||||
|
||||
static const struct udevice_id gcc_sa8775p_of_match[] = {
|
||||
{
|
||||
.compatible = "qcom,sa8775p-gcc",
|
||||
.data = (ulong)&sa8775_gcc_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(gcc_sa8775p) = {
|
||||
.name = "gcc_sa8775p",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = gcc_sa8775p_of_match,
|
||||
.bind = qcom_cc_bind,
|
||||
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
|
||||
};
|
||||
@@ -57,6 +57,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
|
||||
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
|
||||
F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static ulong sm8550_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
@@ -84,6 +94,24 @@ static ulong sm8550_set_rate(struct clk *clk, ulong rate)
|
||||
case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
|
||||
clk_rcg_set_rate(priv->base, 0x39070, 0, 0);
|
||||
return TCXO_DIV2_RATE;
|
||||
case GCC_PCIE_0_AUX_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x6b074,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 16);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_1_AUX_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x8d07c,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 16);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_0_PHY_RCHNG_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
|
||||
clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_1_PHY_RCHNG_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
|
||||
clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src);
|
||||
return freq->freq;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
@@ -182,6 +210,14 @@ static int sm8550_enable(struct clk *clk)
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
|
||||
break;
|
||||
case GCC_PCIE_0_PIPE_CLK:
|
||||
// GCC_PCIE_0_PIPE_CLK_SRC
|
||||
clk_phy_mux_enable(priv->base, 0x6b070, true);
|
||||
break;
|
||||
case GCC_PCIE_1_PIPE_CLK:
|
||||
// GCC_PCIE_1_PIPE_CLK_SRC
|
||||
clk_phy_mux_enable(priv->base, 0x8d078, true);
|
||||
break;
|
||||
}
|
||||
|
||||
qcom_gate_clk_en(priv, clk->id);
|
||||
|
||||
@@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
|
||||
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
|
||||
F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static ulong sm8650_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
@@ -81,6 +91,24 @@ static ulong sm8650_set_rate(struct clk *clk, ulong rate)
|
||||
case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
|
||||
clk_rcg_set_rate(priv->base, 0x39070, 0, 0);
|
||||
return TCXO_DIV2_RATE;
|
||||
case GCC_PCIE_0_AUX_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x6b074,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 16);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_1_AUX_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x8d07c,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 16);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_0_PHY_RCHNG_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
|
||||
clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_1_PHY_RCHNG_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
|
||||
clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src);
|
||||
return freq->freq;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
@@ -179,6 +207,14 @@ static int sm8650_enable(struct clk *clk)
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
|
||||
break;
|
||||
case GCC_PCIE_0_PIPE_CLK:
|
||||
// GCC_PCIE_0_PIPE_CLK_SRC
|
||||
clk_phy_mux_enable(priv->base, 0x6b070, true);
|
||||
break;
|
||||
case GCC_PCIE_1_PIPE_CLK:
|
||||
// GCC_PCIE_1_PIPE_CLK_SRC
|
||||
clk_phy_mux_enable(priv->base, 0x8d078, true);
|
||||
break;
|
||||
}
|
||||
|
||||
qcom_gate_clk_en(priv, clk->id);
|
||||
|
||||
@@ -0,0 +1,402 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Clock drivers for Qualcomm x1e80100
|
||||
*
|
||||
* (C) Copyright 2024 Linaro Ltd.
|
||||
*/
|
||||
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
|
||||
|
||||
#include "clock-qcom.h"
|
||||
|
||||
/* On-board TCXO, TOFIX get from DT */
|
||||
#define TCXO_RATE 38400000
|
||||
|
||||
/* bi_tcxo_div2 divided after RPMh output */
|
||||
#define TCXO_DIV2_RATE (TCXO_RATE / 2)
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
|
||||
F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
|
||||
F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
|
||||
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
|
||||
F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
|
||||
F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
|
||||
F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
|
||||
F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
|
||||
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
|
||||
F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
|
||||
F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
|
||||
F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
|
||||
F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
|
||||
F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
|
||||
F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
|
||||
/* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
|
||||
F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
|
||||
F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
|
||||
F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
|
||||
F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
|
||||
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
|
||||
F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static ulong x1e80100_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
const struct freq_tbl *freq;
|
||||
|
||||
switch (clk->id) {
|
||||
case GCC_QUPV3_WRAP2_S5_CLK: /* UART21 */
|
||||
freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s4_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x1e500,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 16);
|
||||
return freq->freq;
|
||||
case GCC_SDCC2_APPS_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x14018,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_USB30_PRIM_MASTER_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x3902c,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_USB30_PRIM_MOCK_UTMI_CLK:
|
||||
clk_rcg_set_rate(priv->base, 0x39044, 0, 0);
|
||||
return TCXO_DIV2_RATE;
|
||||
case GCC_PCIE_4_AUX_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x6b080,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 16);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_4_PHY_RCHNG_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
|
||||
clk_rcg_set_rate(priv->base, 0x6b064, freq->pre_div, freq->src);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_6A_AUX_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, 0x3108c,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 16);
|
||||
return freq->freq;
|
||||
case GCC_PCIE_6A_PHY_RCHNG_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
|
||||
clk_rcg_set_rate(priv->base, 0x31070, freq->pre_div, freq->src);
|
||||
return freq->freq;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct gate_clk x1e80100_clks[] = {
|
||||
GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)),
|
||||
GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)),
|
||||
GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK, 0x52000, BIT(20)),
|
||||
GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK, 0x52028, BIT(22)),
|
||||
GATE_CLK(GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK, 0x52028, BIT(12)),
|
||||
GATE_CLK(GCC_CNOC_PCIE_NORTH_SF_AXI_CLK, 0x52008, BIT(6)),
|
||||
GATE_CLK(GCC_PCIE_4_AUX_CLK, 0x52008, BIT(3)),
|
||||
GATE_CLK(GCC_PCIE_4_CFG_AHB_CLK, 0x52008, BIT(2)),
|
||||
GATE_CLK(GCC_PCIE_4_MSTR_AXI_CLK, 0x52008, BIT(1)),
|
||||
GATE_CLK(GCC_PCIE_4_PHY_RCHNG_CLK, 0x52000, BIT(22)),
|
||||
GATE_CLK(GCC_PCIE_4_PIPE_CLK, 0x52008, BIT(4)),
|
||||
GATE_CLK(GCC_PCIE_4_SLV_AXI_CLK, 0x52008, BIT(0)),
|
||||
GATE_CLK(GCC_PCIE_4_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)),
|
||||
GATE_CLK(GCC_PCIE_6A_AUX_CLK, 0x52018, BIT(24)),
|
||||
GATE_CLK(GCC_PCIE_6A_CFG_AHB_CLK, 0x52018, BIT(23)),
|
||||
GATE_CLK(GCC_PCIE_6A_MSTR_AXI_CLK, 0x52018, BIT(22)),
|
||||
GATE_CLK(GCC_PCIE_6A_PHY_RCHNG_CLK, 0x52018, BIT(27)),
|
||||
GATE_CLK(GCC_PCIE_6A_PIPE_CLK, 0x52018, BIT(26)),
|
||||
GATE_CLK(GCC_PCIE_6A_SLV_AXI_CLK, 0x52018, BIT(21)),
|
||||
GATE_CLK(GCC_PCIE_6A_SLV_Q2A_AXI_CLK, 0x52018, BIT(20)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, BIT(5)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, BIT(6)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, BIT(7)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, BIT(8)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, BIT(9)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x52010, BIT(10)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP2_S7_CLK, 0x52010, BIT(17)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, BIT(2)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, BIT(1)),
|
||||
GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)),
|
||||
GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)),
|
||||
GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)),
|
||||
GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)),
|
||||
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)),
|
||||
GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)),
|
||||
};
|
||||
|
||||
static int x1e80100_enable(struct clk *clk)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
switch (clk->id) {
|
||||
case GCC_AGGRE_USB3_PRIM_AXI_CLK:
|
||||
qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
|
||||
fallthrough;
|
||||
case GCC_USB30_PRIM_MASTER_CLK:
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
|
||||
break;
|
||||
case GCC_PCIE_4_PIPE_CLK:
|
||||
// GCC_PCIE_4_PIPE_CLK_SRC
|
||||
clk_phy_mux_enable(priv->base, 0x6b07c, true);
|
||||
break;
|
||||
case GCC_PCIE_6A_PIPE_CLK:
|
||||
// GCC_PCIE_6A_PIPE_CLK_SRC
|
||||
clk_phy_mux_enable(priv->base, 0x31088, true);
|
||||
break;
|
||||
}
|
||||
|
||||
qcom_gate_clk_en(priv, clk->id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct qcom_reset_map x1e80100_gcc_resets[] = {
|
||||
[GCC_AV1E_BCR] = { 0x4a000 },
|
||||
[GCC_CAMERA_BCR] = { 0x26000 },
|
||||
[GCC_DISPLAY_BCR] = { 0x27000 },
|
||||
[GCC_GPU_BCR] = { 0x71000 },
|
||||
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
|
||||
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
|
||||
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
|
||||
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
|
||||
[GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
|
||||
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
|
||||
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
|
||||
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
|
||||
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
|
||||
[GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
|
||||
[GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
|
||||
[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
|
||||
[GCC_PCIE_2_PHY_BCR] = { 0xa501c },
|
||||
[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
|
||||
[GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
|
||||
[GCC_PCIE_3_BCR] = { 0x58000 },
|
||||
[GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
|
||||
[GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
|
||||
[GCC_PCIE_3_PHY_BCR] = { 0xab01c },
|
||||
[GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
|
||||
[GCC_PCIE_4_BCR] = { 0x6b000 },
|
||||
[GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
|
||||
[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
|
||||
[GCC_PCIE_4_PHY_BCR] = { 0xb301c },
|
||||
[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
|
||||
[GCC_PCIE_5_BCR] = { 0x2f000 },
|
||||
[GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
|
||||
[GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
|
||||
[GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
|
||||
[GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
|
||||
[GCC_PCIE_6A_BCR] = { 0x31000 },
|
||||
[GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
|
||||
[GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
|
||||
[GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
|
||||
[GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
|
||||
[GCC_PCIE_6B_BCR] = { 0x8d000 },
|
||||
[GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
|
||||
[GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
|
||||
[GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
|
||||
[GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
|
||||
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
|
||||
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
|
||||
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
|
||||
[GCC_PCIE_RSCC_BCR] = { 0xa4000 },
|
||||
[GCC_PDM_BCR] = { 0x33000 },
|
||||
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
|
||||
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
|
||||
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
|
||||
[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
|
||||
[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
|
||||
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
|
||||
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
|
||||
[GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
|
||||
[GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
|
||||
[GCC_SDCC2_BCR] = { 0x14000 },
|
||||
[GCC_SDCC4_BCR] = { 0x16000 },
|
||||
[GCC_UFS_PHY_BCR] = { 0x77000 },
|
||||
[GCC_USB20_PRIM_BCR] = { 0x29000 },
|
||||
[GCC_USB30_MP_BCR] = { 0x17000 },
|
||||
[GCC_USB30_PRIM_BCR] = { 0x39000 },
|
||||
[GCC_USB30_SEC_BCR] = { 0xa1000 },
|
||||
[GCC_USB30_TERT_BCR] = { 0xa2000 },
|
||||
[GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
|
||||
[GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
|
||||
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
|
||||
[GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
|
||||
[GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
|
||||
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
|
||||
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
|
||||
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
|
||||
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
|
||||
[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
|
||||
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
|
||||
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
|
||||
[GCC_USB4_0_BCR] = { 0x9f000 },
|
||||
[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
|
||||
[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
|
||||
[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
|
||||
[GCC_USB4_1_BCR] = { 0x2b000 },
|
||||
[GCC_USB4_2_BCR] = { 0x11000 },
|
||||
[GCC_USB_0_PHY_BCR] = { 0x50020 },
|
||||
[GCC_USB_1_PHY_BCR] = { 0x2a020 },
|
||||
[GCC_USB_2_PHY_BCR] = { 0xa3020 },
|
||||
[GCC_VIDEO_BCR] = { 0x32000 },
|
||||
};
|
||||
|
||||
static const struct qcom_power_map x1e80100_gdscs[] = {
|
||||
[GCC_PCIE_0_TUNNEL_GDSC] = { 0xa0004 },
|
||||
[GCC_PCIE_1_TUNNEL_GDSC] = { 0x2c004 },
|
||||
[GCC_PCIE_2_TUNNEL_GDSC] = { 0x13004 },
|
||||
[GCC_PCIE_3_GDSC] = { 0x58004 },
|
||||
[GCC_PCIE_3_PHY_GDSC] = { 0x3e000 },
|
||||
[GCC_PCIE_4_GDSC] = { 0x6b004 },
|
||||
[GCC_PCIE_4_PHY_GDSC] = { 0x6c000 },
|
||||
[GCC_PCIE_5_GDSC] = { 0x2f004 },
|
||||
[GCC_PCIE_5_PHY_GDSC] = { 0x30000 },
|
||||
[GCC_PCIE_6_PHY_GDSC] = { 0x8e000 },
|
||||
[GCC_PCIE_6A_GDSC] = { 0x31004 },
|
||||
[GCC_PCIE_6B_GDSC] = { 0x8d004 },
|
||||
[GCC_UFS_MEM_PHY_GDSC] = { 0x9e000 },
|
||||
[GCC_UFS_PHY_GDSC] = { 0x77004 },
|
||||
[GCC_USB20_PRIM_GDSC] = { 0x29004 },
|
||||
[GCC_USB30_MP_GDSC] = { 0x17004 },
|
||||
[GCC_USB30_PRIM_GDSC] = { 0x39004 },
|
||||
[GCC_USB30_SEC_GDSC] = { 0xa1004 },
|
||||
[GCC_USB30_TERT_GDSC] = { 0xa2004 },
|
||||
[GCC_USB3_MP_SS0_PHY_GDSC] = { 0x1900c },
|
||||
[GCC_USB3_MP_SS1_PHY_GDSC] = { 0x5400c },
|
||||
[GCC_USB4_0_GDSC] = { 0x9f004 },
|
||||
[GCC_USB4_1_GDSC] = { 0x2b004 },
|
||||
[GCC_USB4_2_GDSC] = { 0x11004 },
|
||||
[GCC_USB_0_PHY_GDSC] = { 0x50024 },
|
||||
[GCC_USB_1_PHY_GDSC] = { 0x2a024 },
|
||||
[GCC_USB_2_PHY_GDSC] = { 0xa3024 },
|
||||
};
|
||||
|
||||
static struct msm_clk_data x1e80100_gcc_data = {
|
||||
.resets = x1e80100_gcc_resets,
|
||||
.num_resets = ARRAY_SIZE(x1e80100_gcc_resets),
|
||||
.clks = x1e80100_clks,
|
||||
.num_clks = ARRAY_SIZE(x1e80100_clks),
|
||||
.power_domains = x1e80100_gdscs,
|
||||
.num_power_domains = ARRAY_SIZE(x1e80100_gdscs),
|
||||
|
||||
.enable = x1e80100_enable,
|
||||
.set_rate = x1e80100_set_rate,
|
||||
};
|
||||
|
||||
static const struct udevice_id gcc_x1e80100_of_match[] = {
|
||||
{
|
||||
.compatible = "qcom,x1e80100-gcc",
|
||||
.data = (ulong)&x1e80100_gcc_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(gcc_x1e80100) = {
|
||||
.name = "gcc_x1e80100",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = gcc_x1e80100_of_match,
|
||||
.bind = qcom_cc_bind,
|
||||
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
|
||||
};
|
||||
|
||||
/* TCSRCC */
|
||||
|
||||
static const struct gate_clk x1e80100_tcsr_clks[] = {
|
||||
GATE_CLK(TCSR_PCIE_2L_4_CLKREF_EN, 0x15100, BIT(0)),
|
||||
GATE_CLK(TCSR_PCIE_2L_5_CLKREF_EN, 0x15104, BIT(0)),
|
||||
GATE_CLK(TCSR_PCIE_8L_CLKREF_EN, 0x15108, BIT(0)),
|
||||
GATE_CLK(TCSR_USB3_MP0_CLKREF_EN, 0x1510c, BIT(0)),
|
||||
GATE_CLK(TCSR_USB3_MP1_CLKREF_EN, 0x15110, BIT(0)),
|
||||
GATE_CLK(TCSR_USB2_1_CLKREF_EN, 0x15114, BIT(0)),
|
||||
GATE_CLK(TCSR_UFS_PHY_CLKREF_EN, 0x15118, BIT(0)),
|
||||
GATE_CLK(TCSR_USB4_1_CLKREF_EN, 0x15120, BIT(0)),
|
||||
GATE_CLK(TCSR_USB4_2_CLKREF_EN, 0x15124, BIT(0)),
|
||||
GATE_CLK(TCSR_USB2_2_CLKREF_EN, 0x15128, BIT(0)),
|
||||
GATE_CLK(TCSR_PCIE_4L_CLKREF_EN, 0x1512c, BIT(0)),
|
||||
GATE_CLK(TCSR_EDP_CLKREF_EN, 0x15130, BIT(0)),
|
||||
};
|
||||
|
||||
static struct msm_clk_data x1e80100_tcsrcc_data = {
|
||||
.clks = x1e80100_tcsr_clks,
|
||||
.num_clks = ARRAY_SIZE(x1e80100_tcsr_clks),
|
||||
};
|
||||
|
||||
static int tcsrcc_x1e80100_clk_enable(struct clk *clk)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
qcom_gate_clk_en(priv, clk->id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ulong tcsrcc_x1e80100_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return TCXO_RATE;
|
||||
}
|
||||
|
||||
static int tcsrcc_x1e80100_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
|
||||
struct msm_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->base = dev_read_addr(dev);
|
||||
if (priv->base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
priv->data = data;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops tcsrcc_x1e80100_clk_ops = {
|
||||
.enable = tcsrcc_x1e80100_clk_enable,
|
||||
.get_rate = tcsrcc_x1e80100_clk_get_rate,
|
||||
};
|
||||
|
||||
static const struct udevice_id tcsrcc_x1e80100_of_match[] = {
|
||||
{
|
||||
.compatible = "qcom,x1e80100-tcsr",
|
||||
.data = (ulong)&x1e80100_tcsrcc_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(tcsrcc_x1e80100) = {
|
||||
.name = "tcsrcc_x1e80100",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = tcsrcc_x1e80100_of_match,
|
||||
.ops = &tcsrcc_x1e80100_clk_ops,
|
||||
.priv_auto = sizeof(struct msm_clk_priv),
|
||||
.probe = tcsrcc_x1e80100_clk_probe,
|
||||
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
|
||||
};
|
||||
@@ -371,6 +371,14 @@ config PCIE_DW_MESON
|
||||
Say Y here if you want to enable DW PCIe controller support on
|
||||
Amlogic SoCs.
|
||||
|
||||
config PCIE_DW_QCOM
|
||||
bool "Qualcomm DesignWare based PCIe controller"
|
||||
depends on ARCH_SNAPDRAGON
|
||||
select PCIE_DW_COMMON
|
||||
help
|
||||
Say Y here if you want to enable DW PCIe controller support on
|
||||
Qualcomm SoCs.
|
||||
|
||||
config PCIE_ROCKCHIP
|
||||
bool "Enable Rockchip PCIe driver"
|
||||
depends on ARCH_ROCKCHIP
|
||||
|
||||
@@ -47,6 +47,7 @@ obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie_mediatek_gen3.o
|
||||
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
|
||||
obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o
|
||||
obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o
|
||||
obj-$(CONFIG_PCIE_DW_QCOM) += pcie_dw_qcom.o
|
||||
obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
|
||||
obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
|
||||
obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
|
||||
|
||||
@@ -267,6 +267,48 @@ int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf,
|
||||
pcie->io.bus_start, pcie->io.size);
|
||||
}
|
||||
|
||||
/*
|
||||
* These interfaces resemble the pci_find_*capability() interfaces, but these
|
||||
* are for configuring host controllers, which are bridges *to* PCI devices but
|
||||
* are not PCI devices themselves.
|
||||
*/
|
||||
static u8 pcie_dw_find_next_cap(struct pcie_dw *pci, u8 cap_ptr, u8 cap)
|
||||
{
|
||||
u8 cap_id, next_cap_ptr;
|
||||
u32 val;
|
||||
u16 reg;
|
||||
|
||||
if (!cap_ptr)
|
||||
return 0;
|
||||
|
||||
val = readl(pci->dbi_base + (cap_ptr & ~0x3));
|
||||
reg = pci_conv_32_to_size(val, cap_ptr, 2);
|
||||
cap_id = (reg & 0x00ff);
|
||||
|
||||
if (cap_id > PCI_CAP_ID_MAX)
|
||||
return 0;
|
||||
|
||||
if (cap_id == cap)
|
||||
return cap_ptr;
|
||||
|
||||
next_cap_ptr = (reg & 0xff00) >> 8;
|
||||
return pcie_dw_find_next_cap(pci, next_cap_ptr, cap);
|
||||
}
|
||||
|
||||
u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap)
|
||||
{
|
||||
u8 next_cap_ptr;
|
||||
u32 val;
|
||||
u16 reg;
|
||||
|
||||
val = readl(pci->dbi_base + (PCI_CAPABILITY_LIST & ~0x3));
|
||||
reg = pci_conv_32_to_size(val, PCI_CAPABILITY_LIST, 2);
|
||||
|
||||
next_cap_ptr = (reg & 0x00ff);
|
||||
|
||||
return pcie_dw_find_next_cap(pci, next_cap_ptr, cap);
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
|
||||
*
|
||||
|
||||
@@ -139,6 +139,8 @@ int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, u
|
||||
int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value,
|
||||
enum pci_size_t size);
|
||||
|
||||
u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap);
|
||||
|
||||
static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
@@ -0,0 +1,571 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <generic-phy.h>
|
||||
#include <pci.h>
|
||||
#include <u-boot/crc.h>
|
||||
#include <power-domain.h>
|
||||
#include <reset.h>
|
||||
#include <syscon.h>
|
||||
#include <malloc.h>
|
||||
#include <power/regulator.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#include "pcie_dw_common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct qcom_pcie;
|
||||
|
||||
struct qcom_pcie_ops {
|
||||
int (*config_sid)(struct qcom_pcie *priv);
|
||||
};
|
||||
|
||||
#define NUM_SUPPLIES 2
|
||||
|
||||
struct qcom_pcie {
|
||||
/* Must be first member of the struct */
|
||||
struct pcie_dw dw;
|
||||
void *parf;
|
||||
struct phy phy;
|
||||
struct reset_ctl_bulk rsts;
|
||||
struct clk_bulk clks;
|
||||
struct gpio_desc rst_gpio;
|
||||
struct qcom_pcie_ops *ops;
|
||||
struct udevice *vregs[NUM_SUPPLIES];
|
||||
};
|
||||
|
||||
/* PARF registers */
|
||||
#define PARF_SYS_CTRL 0x00
|
||||
#define PARF_PM_CTRL 0x20
|
||||
#define PARF_PCS_DEEMPH 0x34
|
||||
#define PARF_PCS_SWING 0x38
|
||||
#define PARF_PHY_CTRL 0x40
|
||||
#define PARF_PHY_REFCLK 0x4c
|
||||
#define PARF_CONFIG_BITS 0x50
|
||||
#define PARF_DBI_BASE_ADDR 0x168
|
||||
#define PARF_MHI_CLOCK_RESET_CTRL 0x174
|
||||
#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
|
||||
#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
|
||||
#define PARF_Q2A_FLUSH 0x1ac
|
||||
#define PARF_LTSSM 0x1b0
|
||||
#define PARF_SID_OFFSET 0x234
|
||||
#define PARF_BDF_TRANSLATE_CFG 0x24c
|
||||
#define PARF_SLV_ADDR_SPACE_SIZE 0x358
|
||||
#define PARF_DEVICE_TYPE 0x1000
|
||||
#define PARF_BDF_TO_SID_TABLE_N 0x2000
|
||||
|
||||
/* ELBI registers */
|
||||
#define ELBI_SYS_CTRL 0x04
|
||||
|
||||
/* DBI registers */
|
||||
#define AXI_MSTR_RESP_COMP_CTRL0 0x818
|
||||
#define AXI_MSTR_RESP_COMP_CTRL1 0x81c
|
||||
#define MISC_CONTROL_1_REG 0x8bc
|
||||
|
||||
/* MHI registers */
|
||||
#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
|
||||
#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
|
||||
#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
|
||||
#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
|
||||
#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
|
||||
|
||||
/* PARF_SYS_CTRL register fields */
|
||||
#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
|
||||
#define MST_WAKEUP_EN BIT(13)
|
||||
#define SLV_WAKEUP_EN BIT(12)
|
||||
#define MSTR_ACLK_CGC_DIS BIT(10)
|
||||
#define SLV_ACLK_CGC_DIS BIT(9)
|
||||
#define CORE_CLK_CGC_DIS BIT(6)
|
||||
#define AUX_PWR_DET BIT(4)
|
||||
#define L23_CLK_RMV_DIS BIT(2)
|
||||
#define L1_CLK_RMV_DIS BIT(1)
|
||||
|
||||
/* PARF_PM_CTRL register fields */
|
||||
#define REQ_NOT_ENTR_L1 BIT(5)
|
||||
|
||||
/* PARF_PCS_DEEMPH register fields */
|
||||
#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
|
||||
#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
|
||||
#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
|
||||
|
||||
/* PARF_PCS_SWING register fields */
|
||||
#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
|
||||
#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
|
||||
|
||||
/* PARF_PHY_CTRL register fields */
|
||||
#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
|
||||
#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
|
||||
#define PHY_TEST_PWR_DOWN BIT(0)
|
||||
|
||||
/* PARF_PHY_REFCLK register fields */
|
||||
#define PHY_REFCLK_SSP_EN BIT(16)
|
||||
#define PHY_REFCLK_USE_PAD BIT(12)
|
||||
|
||||
/* PARF_CONFIG_BITS register fields */
|
||||
#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
|
||||
|
||||
/* PARF_SLV_ADDR_SPACE_SIZE register value */
|
||||
#define SLV_ADDR_SPACE_SZ 0x10000000
|
||||
|
||||
/* PARF_MHI_CLOCK_RESET_CTRL register fields */
|
||||
#define AHB_CLK_EN BIT(0)
|
||||
#define MSTR_AXI_CLK_EN BIT(1)
|
||||
#define BYPASS BIT(4)
|
||||
|
||||
/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
|
||||
#define EN BIT(31)
|
||||
|
||||
/* PARF_LTSSM register fields */
|
||||
#define LTSSM_EN BIT(8)
|
||||
|
||||
/* PARF_DEVICE_TYPE register fields */
|
||||
#define DEVICE_TYPE_RC 0x4
|
||||
|
||||
/* ELBI_SYS_CTRL register fields */
|
||||
#define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
|
||||
|
||||
/* AXI_MSTR_RESP_COMP_CTRL0 register fields */
|
||||
#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
|
||||
#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
|
||||
|
||||
/* AXI_MSTR_RESP_COMP_CTRL1 register fields */
|
||||
#define CFG_BRIDGE_SB_INIT BIT(0)
|
||||
|
||||
/* MISC_CONTROL_1_REG register fields */
|
||||
#define DBI_RO_WR_EN 1
|
||||
|
||||
/* PCI_EXP_SLTCAP register fields */
|
||||
#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
|
||||
#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
|
||||
#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
|
||||
PCI_EXP_SLTCAP_PCP | \
|
||||
PCI_EXP_SLTCAP_MRLSP | \
|
||||
PCI_EXP_SLTCAP_AIP | \
|
||||
PCI_EXP_SLTCAP_PIP | \
|
||||
PCI_EXP_SLTCAP_HPS | \
|
||||
PCI_EXP_SLTCAP_HPC | \
|
||||
PCI_EXP_SLTCAP_EIP | \
|
||||
PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
|
||||
PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
|
||||
|
||||
#define PERST_DELAY_US 1000
|
||||
|
||||
#define LINK_WAIT_MAX_RETRIES 10
|
||||
#define LINK_WAIT_USLEEP 100000
|
||||
|
||||
#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
|
||||
|
||||
#define CRC8_TABLE_SIZE 256
|
||||
|
||||
static bool qcom_pcie_wait_link_up(struct qcom_pcie *priv)
|
||||
{
|
||||
u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
|
||||
unsigned int cnt = 0;
|
||||
u16 val;
|
||||
|
||||
do {
|
||||
val = readw(priv->dw.dbi_base + offset + PCI_EXP_LNKSTA);
|
||||
|
||||
if ((val & PCI_EXP_LNKSTA_DLLLA))
|
||||
return true;
|
||||
cnt++;
|
||||
|
||||
udelay(LINK_WAIT_USLEEP);
|
||||
} while (cnt < LINK_WAIT_MAX_RETRIES);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static void qcom_pcie_clear_aspm_l0s(struct qcom_pcie *priv)
|
||||
{
|
||||
u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
|
||||
u32 val;
|
||||
|
||||
dw_pcie_dbi_write_enable(&priv->dw, true);
|
||||
|
||||
val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
|
||||
val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
|
||||
writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
|
||||
|
||||
dw_pcie_dbi_write_enable(&priv->dw, false);
|
||||
}
|
||||
|
||||
static void qcom_pcie_clear_hpc(struct qcom_pcie *priv)
|
||||
{
|
||||
u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
|
||||
u32 val;
|
||||
|
||||
dw_pcie_dbi_write_enable(&priv->dw, true);
|
||||
|
||||
val = readl(priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);
|
||||
val &= ~PCI_EXP_SLTCAP_HPC;
|
||||
writel(val, priv->dw.dbi_base + offset + PCI_EXP_SLTCAP);
|
||||
|
||||
dw_pcie_dbi_write_enable(&priv->dw, false);
|
||||
}
|
||||
|
||||
static void qcom_pcie_set_lanes(struct qcom_pcie *priv, unsigned int lanes)
|
||||
{
|
||||
u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP);
|
||||
u32 val;
|
||||
|
||||
val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
|
||||
val &= ~PCI_EXP_LNKCAP_MLW;
|
||||
val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, lanes);
|
||||
writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP);
|
||||
}
|
||||
|
||||
static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *priv)
|
||||
{
|
||||
/* iommu map structure */
|
||||
struct {
|
||||
u32 bdf;
|
||||
u32 phandle;
|
||||
u32 smmu_sid;
|
||||
u32 smmu_sid_len;
|
||||
} *map;
|
||||
void *bdf_to_sid_base = priv->parf + PARF_BDF_TO_SID_TABLE_N;
|
||||
int i, nr_map, size = 0;
|
||||
u32 smmu_sid_base;
|
||||
|
||||
dev_read_prop(priv->dw.dev, "iommu-map", &size);
|
||||
if (!size)
|
||||
return 0;
|
||||
|
||||
map = malloc(size);
|
||||
if (!map)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_read_u32_array(priv->dw.dev, "iommu-map", (u32 *)map, size / sizeof(u32));
|
||||
|
||||
nr_map = size / (sizeof(*map));
|
||||
|
||||
/* Registers need to be zero out first */
|
||||
memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
|
||||
|
||||
/* Extract the SMMU SID base from the first entry of iommu-map */
|
||||
smmu_sid_base = map[0].smmu_sid;
|
||||
|
||||
/* Look for an available entry to hold the mapping */
|
||||
for (i = 0; i < nr_map; i++) {
|
||||
__be16 bdf_be = cpu_to_be16(map[i].bdf);
|
||||
u32 val;
|
||||
u8 hash;
|
||||
|
||||
hash = crc8(QCOM_PCIE_CRC8_POLYNOMIAL, (u8 *)&bdf_be, sizeof(bdf_be));
|
||||
|
||||
val = readl(bdf_to_sid_base + hash * sizeof(u32));
|
||||
|
||||
/* If the register is already populated, look for next available entry */
|
||||
while (val) {
|
||||
u8 current_hash = hash++;
|
||||
u8 next_mask = 0xff;
|
||||
|
||||
/* If NEXT field is NULL then update it with next hash */
|
||||
if (!(val & next_mask)) {
|
||||
val |= (u32)hash;
|
||||
writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
|
||||
}
|
||||
|
||||
val = readl(bdf_to_sid_base + hash * sizeof(u32));
|
||||
}
|
||||
|
||||
/* BDF [31:16] | SID [15:8] | NEXT [7:0] */
|
||||
val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
|
||||
writel(val, bdf_to_sid_base + hash * sizeof(u32));
|
||||
}
|
||||
|
||||
free(map);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void qcom_pcie_configure(struct qcom_pcie *priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
dw_pcie_dbi_write_enable(&priv->dw, true);
|
||||
|
||||
val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
|
||||
val &= ~PORT_LINK_FAST_LINK_MODE;
|
||||
val |= PORT_LINK_DLL_LINK_EN;
|
||||
val &= ~PORT_LINK_MODE_MASK;
|
||||
val |= PORT_LINK_MODE_2_LANES;
|
||||
writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
|
||||
|
||||
val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
||||
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
|
||||
val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
|
||||
writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
||||
|
||||
qcom_pcie_set_lanes(priv, 2);
|
||||
|
||||
dw_pcie_dbi_write_enable(&priv->dw, false);
|
||||
}
|
||||
|
||||
static int qcom_pcie_init_port(struct udevice *dev)
|
||||
{
|
||||
struct qcom_pcie *priv = dev_get_priv(dev);
|
||||
int vreg, ret;
|
||||
u32 val;
|
||||
|
||||
dm_gpio_set_value(&priv->rst_gpio, 1);
|
||||
udelay(PERST_DELAY_US);
|
||||
|
||||
ret = generic_phy_init(&priv->phy);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to init phy (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
udelay(PERST_DELAY_US);
|
||||
|
||||
for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
|
||||
ret = regulator_set_enable(priv->vregs[vreg], true);
|
||||
if (ret && ret != -ENOSYS)
|
||||
dev_warn(dev, "failed to enable regulator %d (%d)\n", vreg, ret);
|
||||
}
|
||||
|
||||
ret = clk_enable_bulk(&priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable clocks (%d)\n", ret);
|
||||
goto err_power_off_phy;
|
||||
}
|
||||
|
||||
ret = reset_assert_bulk(&priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to assert resets (%d)\n", ret);
|
||||
goto err_disable_clks;
|
||||
}
|
||||
|
||||
udelay(PERST_DELAY_US);
|
||||
|
||||
ret = reset_deassert_bulk(&priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to deassert resets (%d)\n", ret);
|
||||
goto err_power_off_phy;
|
||||
}
|
||||
|
||||
udelay(PERST_DELAY_US);
|
||||
|
||||
/* configure PCIe to RC mode */
|
||||
writel(DEVICE_TYPE_RC, priv->parf + PARF_DEVICE_TYPE);
|
||||
|
||||
/* enable PCIe clocks and resets */
|
||||
val = readl(priv->parf + PARF_PHY_CTRL);
|
||||
val &= ~PHY_TEST_PWR_DOWN;
|
||||
writel(val, priv->parf + PARF_PHY_CTRL);
|
||||
|
||||
/* change DBI base address */
|
||||
writel(0, priv->parf + PARF_DBI_BASE_ADDR);
|
||||
|
||||
/* MAC PHY_POWERDOWN MUX DISABLE */
|
||||
val = readl(priv->parf + PARF_SYS_CTRL);
|
||||
val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
|
||||
writel(val, priv->parf + PARF_SYS_CTRL);
|
||||
|
||||
val = readl(priv->parf + PARF_MHI_CLOCK_RESET_CTRL);
|
||||
val |= BYPASS;
|
||||
writel(val, priv->parf + PARF_MHI_CLOCK_RESET_CTRL);
|
||||
|
||||
/* Enable L1 and L1SS */
|
||||
val = readl(priv->parf + PARF_PM_CTRL);
|
||||
val &= ~REQ_NOT_ENTR_L1;
|
||||
writel(val, priv->parf + PARF_PM_CTRL);
|
||||
|
||||
val = readl(priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
|
||||
val |= EN;
|
||||
writel(val, priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
|
||||
|
||||
ret = generic_phy_power_on(&priv->phy);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to power on phy (%d)\n", ret);
|
||||
goto err_exit_phy;
|
||||
}
|
||||
|
||||
qcom_pcie_clear_aspm_l0s(priv);
|
||||
qcom_pcie_clear_hpc(priv);
|
||||
|
||||
mdelay(100);
|
||||
dm_gpio_set_value(&priv->rst_gpio, 0);
|
||||
udelay(PERST_DELAY_US);
|
||||
|
||||
if (priv->ops && priv->ops->config_sid) {
|
||||
ret = priv->ops->config_sid(priv);
|
||||
if (ret)
|
||||
goto err_deassert_bulk;
|
||||
}
|
||||
|
||||
qcom_pcie_configure(priv);
|
||||
|
||||
pcie_dw_setup_host(&priv->dw);
|
||||
|
||||
/* enable link training */
|
||||
val = readl(priv->parf + PARF_LTSSM);
|
||||
val |= LTSSM_EN;
|
||||
writel(val, priv->parf + PARF_LTSSM);
|
||||
|
||||
return 0;
|
||||
err_deassert_bulk:
|
||||
reset_assert_bulk(&priv->rsts);
|
||||
err_disable_clks:
|
||||
clk_disable_bulk(&priv->clks);
|
||||
err_power_off_phy:
|
||||
generic_phy_power_off(&priv->phy);
|
||||
err_exit_phy:
|
||||
generic_phy_exit(&priv->phy);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const char *qcom_pcie_vregs[NUM_SUPPLIES] = {
|
||||
"vdda-supply",
|
||||
"vddpe-3v3-supply",
|
||||
};
|
||||
|
||||
static int qcom_pcie_parse_dt(struct udevice *dev)
|
||||
{
|
||||
struct qcom_pcie *priv = dev_get_priv(dev);
|
||||
int vreg, ret;
|
||||
|
||||
priv->dw.dbi_base = dev_read_addr_name_ptr(dev, "dbi");
|
||||
if (!priv->dw.dbi_base)
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
|
||||
|
||||
priv->dw.atu_base = dev_read_addr_name_ptr(dev, "atu");
|
||||
if (!priv->dw.atu_base)
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(dev, "ATU address is 0x%p\n", priv->dw.atu_base);
|
||||
|
||||
priv->parf = dev_read_addr_name_ptr(dev, "parf");
|
||||
if (!priv->parf)
|
||||
return -EINVAL;
|
||||
|
||||
dev_dbg(dev, "PARF address is 0x%p\n", priv->parf);
|
||||
|
||||
ret = gpio_request_by_name(dev, "perst-gpios", 0,
|
||||
&priv->rst_gpio, GPIOD_IS_OUT);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to find reset-gpios property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_get_bulk(dev, &priv->rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get resets (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_bulk(dev, &priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get clocks (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = generic_phy_get_by_index(dev, 0, &priv->phy);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get pcie phy (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) {
|
||||
ret = device_get_supply_regulator(dev, qcom_pcie_vregs[vreg], &priv->vregs[vreg]);
|
||||
if (ret)
|
||||
dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_pcie_probe() - Probe the PCIe bus for active link
|
||||
*
|
||||
* @dev: A pointer to the device being operated on
|
||||
*
|
||||
* Probe for an active link on the PCIe bus and configure the controller
|
||||
* to enable this port.
|
||||
*
|
||||
* Return: 0 on success, else -ENODEV
|
||||
*/
|
||||
static int qcom_pcie_probe(struct udevice *dev)
|
||||
{
|
||||
struct qcom_pcie *priv = dev_get_priv(dev);
|
||||
struct udevice *ctlr = pci_get_controller(dev);
|
||||
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
||||
int ret = 0;
|
||||
|
||||
priv->dw.first_busno = dev_seq(dev);
|
||||
priv->dw.dev = dev;
|
||||
|
||||
ret = qcom_pcie_parse_dt(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_pcie_init_port(dev);
|
||||
if (ret) {
|
||||
dm_gpio_free(dev, &priv->rst_gpio);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (qcom_pcie_wait_link_up(priv))
|
||||
printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
|
||||
dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
|
||||
pcie_dw_get_link_width(&priv->dw),
|
||||
hose->first_busno);
|
||||
else
|
||||
printf("PCIE-%d: Link up timeout\n", dev_seq(dev));
|
||||
|
||||
return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
|
||||
PCIE_ATU_REGION_INDEX0,
|
||||
PCIE_ATU_TYPE_MEM,
|
||||
priv->dw.mem.phys_start,
|
||||
priv->dw.mem.bus_start,
|
||||
priv->dw.mem.size);
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops qcom_pcie_ops = {
|
||||
.read_config = pcie_dw_read_config,
|
||||
.write_config = pcie_dw_write_config,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_ops ops_1_9_0 = {
|
||||
.config_sid = qcom_pcie_config_sid_1_9_0,
|
||||
};
|
||||
|
||||
static const struct udevice_id qcom_pcie_ids[] = {
|
||||
{ .compatible = "qcom,pcie-sa8540p", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc7280", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc8180x", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sc8280xp", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sdm845" },
|
||||
{ .compatible = "qcom,pcie-sdx55", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8150", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8250", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8350", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-sm8550", .data = (ulong)&ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-x1e80100", .data = (ulong)&ops_1_9_0 },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(qcom_dw_pcie) = {
|
||||
.name = "pcie_dw_qcom",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = qcom_pcie_ids,
|
||||
.ops = &qcom_pcie_ops,
|
||||
.probe = qcom_pcie_probe,
|
||||
.priv_auto = sizeof(struct qcom_pcie),
|
||||
};
|
||||
@@ -12,6 +12,12 @@ config PHY_QCOM_IPQ4019_USB
|
||||
help
|
||||
Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
|
||||
|
||||
config PHY_QCOM_QMP_PCIE
|
||||
tristate "Qualcomm QMP PCIe PHY driver"
|
||||
depends on PHY && ARCH_SNAPDRAGON
|
||||
help
|
||||
Enable this to support the PCIe QMP PHY on various Qualcomm chipsets.
|
||||
|
||||
config PHY_QCOM_QMP_UFS
|
||||
tristate "Qualcomm QMP UFS PHY driver"
|
||||
depends on PHY && ARCH_SNAPDRAGON
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
|
||||
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
|
||||
obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
|
||||
obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o
|
||||
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o
|
||||
|
||||
@@ -0,0 +1,123 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCIE_QHP_H_
|
||||
#define QCOM_PHY_QMP_PCIE_QHP_H_
|
||||
|
||||
/* PCIE GEN3 COM registers */
|
||||
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
|
||||
#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
|
||||
#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
|
||||
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
|
||||
#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
|
||||
#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
|
||||
#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
|
||||
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
|
||||
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
|
||||
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
|
||||
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
|
||||
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
|
||||
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
|
||||
#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
|
||||
#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
|
||||
#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
|
||||
#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
|
||||
#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
|
||||
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
|
||||
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
|
||||
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
|
||||
#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
|
||||
#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
|
||||
#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
|
||||
#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
|
||||
#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
|
||||
#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
|
||||
#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
|
||||
#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
|
||||
#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
|
||||
#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
|
||||
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
|
||||
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
|
||||
|
||||
/* PCIE GEN3 QHP Lane registers */
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
|
||||
#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
|
||||
#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
|
||||
#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
|
||||
#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
|
||||
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
|
||||
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
|
||||
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
|
||||
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
|
||||
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
|
||||
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
|
||||
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
|
||||
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
|
||||
#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
|
||||
#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
|
||||
#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
|
||||
#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
|
||||
#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
|
||||
#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
|
||||
#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
|
||||
#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
|
||||
#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
|
||||
#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
|
||||
#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
|
||||
#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
|
||||
#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
|
||||
#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
|
||||
#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
|
||||
#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
|
||||
#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
|
||||
#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
|
||||
#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
|
||||
#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
|
||||
#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
|
||||
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
|
||||
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
|
||||
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
|
||||
#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
|
||||
#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
|
||||
#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
|
||||
#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
|
||||
#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
|
||||
#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
|
||||
#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
|
||||
#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
|
||||
#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
|
||||
#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
|
||||
#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
|
||||
|
||||
/* PCIE GEN3 PCS registers */
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
|
||||
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
|
||||
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
|
||||
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
|
||||
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_
|
||||
#define QCOM_PHY_QMP_PCS_MISC_V3_H_
|
||||
|
||||
/* Only for QMP V3 PHY - PCS_MISC registers */
|
||||
#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
|
||||
#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
|
||||
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,72 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V4_H_
|
||||
|
||||
/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
|
||||
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10
|
||||
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
|
||||
#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18
|
||||
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
|
||||
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20
|
||||
#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24
|
||||
#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28
|
||||
#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c
|
||||
#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30
|
||||
#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34
|
||||
#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38
|
||||
#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c
|
||||
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
|
||||
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44
|
||||
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
|
||||
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c
|
||||
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
|
||||
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c
|
||||
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
|
||||
#define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94
|
||||
#define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98
|
||||
#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c
|
||||
#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
|
||||
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8
|
||||
#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec
|
||||
#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
|
||||
|
||||
#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
|
||||
#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
|
||||
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
|
||||
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
|
||||
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
|
||||
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
|
||||
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
|
||||
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
|
||||
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - PCS_PCIE registers */
|
||||
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
|
||||
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
|
||||
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
|
||||
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
|
||||
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
|
||||
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
|
||||
|
||||
/* Only for QMP V5_20 PHY - PCIe PCS registers */
|
||||
#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
|
||||
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
|
||||
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
|
||||
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
|
||||
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
|
||||
#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
|
||||
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
|
||||
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
|
||||
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
|
||||
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
|
||||
#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24
|
||||
#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
|
||||
|
||||
/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
|
||||
#define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4
|
||||
#define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4
|
||||
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
|
||||
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
|
||||
#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
|
||||
#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
|
||||
|
||||
/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */
|
||||
#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
|
||||
#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
|
||||
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
|
||||
#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
|
||||
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
|
||||
#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0
|
||||
#define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4
|
||||
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
|
||||
#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
|
||||
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
|
||||
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
|
||||
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
|
||||
#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac
|
||||
#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V5_H_
|
||||
#define QCOM_PHY_QMP_PCS_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - USB/PCIe PCS registers */
|
||||
#define QPHY_V5_PCS_SW_RESET 0x000
|
||||
#define QPHY_V5_PCS_PCS_STATUS1 0x014
|
||||
#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
|
||||
#define QPHY_V5_PCS_START_CONTROL 0x044
|
||||
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
|
||||
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
|
||||
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
|
||||
#define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
|
||||
#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
|
||||
#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
|
||||
#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
|
||||
#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
|
||||
#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
|
||||
#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
|
||||
#define QPHY_V5_PCS_CDR_RESET_TIME 0x1b0
|
||||
#define QPHY_V5_PCS_RX_CONFIG 0x1b0
|
||||
#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 0x1c0
|
||||
#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 0x1c4
|
||||
#define QPHY_V5_PCS_PCS_TX_RX_CONFIG 0x1d0
|
||||
#define QPHY_V5_PCS_EQ_CONFIG1 0x1dc
|
||||
#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
|
||||
#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
|
||||
#define QPHY_V5_PCS_EQ_CONFIG5 0x1ec
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V6_H_
|
||||
#define QCOM_PHY_QMP_PCS_V6_H_
|
||||
|
||||
/* Only for QMP V6 PHY - USB/PCIe PCS registers */
|
||||
#define QPHY_V6_PCS_SW_RESET 0x000
|
||||
#define QPHY_V6_PCS_PCS_STATUS1 0x014
|
||||
#define QPHY_V6_PCS_POWER_DOWN_CONTROL 0x040
|
||||
#define QPHY_V6_PCS_START_CONTROL 0x044
|
||||
#define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x090
|
||||
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0x0c4
|
||||
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0x0c8
|
||||
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc
|
||||
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8
|
||||
#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0dc
|
||||
#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188
|
||||
#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
|
||||
#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
|
||||
#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198
|
||||
#define QPHY_V6_PCS_CDR_RESET_TIME 0x1b0
|
||||
#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
|
||||
#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
|
||||
#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
|
||||
#define QPHY_V6_PCS_EQ_CONFIG1 0x1dc
|
||||
#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0
|
||||
#define QPHY_V6_PCS_EQ_CONFIG5 0x1ec
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
|
||||
#define QCOM_PHY_QMP_PCS_V6_20_H_
|
||||
|
||||
/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
|
||||
#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
|
||||
#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
|
||||
#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
|
||||
#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
|
||||
#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
|
||||
#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
|
||||
#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
|
||||
#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,124 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_COM_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - QSERDES COM registers */
|
||||
#define QSERDES_V5_COM_ATB_SEL1 0x000
|
||||
#define QSERDES_V5_COM_ATB_SEL2 0x004
|
||||
#define QSERDES_V5_COM_FREQ_UPDATE 0x008
|
||||
#define QSERDES_V5_COM_BG_TIMER 0x00c
|
||||
#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
|
||||
#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
|
||||
#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
|
||||
#define QSERDES_V5_COM_SSC_PER1 0x01c
|
||||
#define QSERDES_V5_COM_SSC_PER2 0x020
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
|
||||
#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038
|
||||
#define QSERDES_V5_COM_POST_DIV 0x03c
|
||||
#define QSERDES_V5_COM_POST_DIV_MUX 0x040
|
||||
#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
|
||||
#define QSERDES_V5_COM_CLK_ENABLE1 0x048
|
||||
#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c
|
||||
#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
|
||||
#define QSERDES_V5_COM_PLL_EN 0x054
|
||||
#define QSERDES_V5_COM_PLL_IVCO 0x058
|
||||
#define QSERDES_V5_COM_CMN_IETRIM 0x05c
|
||||
#define QSERDES_V5_COM_CMN_IPTRIM 0x060
|
||||
#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064
|
||||
#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068
|
||||
#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c
|
||||
#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070
|
||||
#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
|
||||
#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
|
||||
#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
|
||||
#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
|
||||
#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
|
||||
#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
|
||||
#define QSERDES_V5_COM_PLL_CNTRL 0x08c
|
||||
#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090
|
||||
#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
|
||||
#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098
|
||||
#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c
|
||||
#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0
|
||||
#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
|
||||
#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
|
||||
#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
|
||||
#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
|
||||
#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
|
||||
#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
|
||||
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
|
||||
#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0
|
||||
#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
|
||||
#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
|
||||
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
|
||||
#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4
|
||||
#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
|
||||
#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
|
||||
#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
|
||||
#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100
|
||||
#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104
|
||||
#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
|
||||
#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
|
||||
#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
|
||||
#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
|
||||
#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
|
||||
#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120
|
||||
#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130
|
||||
#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134
|
||||
#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138
|
||||
#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c
|
||||
#define QSERDES_V5_COM_CMN_STATUS 0x140
|
||||
#define QSERDES_V5_COM_RESET_SM_STATUS 0x144
|
||||
#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148
|
||||
#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c
|
||||
#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150
|
||||
#define QSERDES_V5_COM_CLK_SELECT 0x154
|
||||
#define QSERDES_V5_COM_HSCLK_SEL 0x158
|
||||
#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
|
||||
#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160
|
||||
#define QSERDES_V5_COM_PLL_ANALOG 0x164
|
||||
#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
|
||||
#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
|
||||
#define QSERDES_V5_COM_SW_RESET 0x170
|
||||
#define QSERDES_V5_COM_CORE_CLK_EN 0x174
|
||||
#define QSERDES_V5_COM_C_READY_STATUS 0x178
|
||||
#define QSERDES_V5_COM_CMN_CONFIG 0x17c
|
||||
#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180
|
||||
#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184
|
||||
#define QSERDES_V5_COM_DEBUG_BUS0 0x188
|
||||
#define QSERDES_V5_COM_DEBUG_BUS1 0x18c
|
||||
#define QSERDES_V5_COM_DEBUG_BUS2 0x190
|
||||
#define QSERDES_V5_COM_DEBUG_BUS3 0x194
|
||||
#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198
|
||||
#define QSERDES_V5_COM_CMN_MISC1 0x19c
|
||||
#define QSERDES_V5_COM_CMN_MODE 0x1a0
|
||||
#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
|
||||
#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
|
||||
#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
|
||||
#define QSERDES_V5_COM_RESERVED_1 0x1c0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
|
||||
|
||||
#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
|
||||
#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
|
||||
#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
|
||||
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
|
||||
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
|
||||
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
|
||||
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
|
||||
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
|
||||
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
|
||||
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
|
||||
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
|
||||
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
|
||||
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
|
||||
#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,231 @@
|
||||
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
|
||||
|
||||
/* Only for QMP V5 PHY - TX registers */
|
||||
#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
|
||||
#define QSERDES_V5_TX_BIST_INVERT 0x004
|
||||
#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
|
||||
#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
|
||||
#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
|
||||
#define QSERDES_V5_TX_TX_DRV_LVL 0x014
|
||||
#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
|
||||
#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
|
||||
#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
|
||||
#define QSERDES_V5_TX_TX_BAND 0x024
|
||||
#define QSERDES_V5_TX_SLEW_CNTL 0x028
|
||||
#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c
|
||||
#define QSERDES_V5_TX_LPB_EN 0x030
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c
|
||||
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040
|
||||
#define QSERDES_V5_TX_PERL_LENGTH1 0x044
|
||||
#define QSERDES_V5_TX_PERL_LENGTH2 0x048
|
||||
#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c
|
||||
#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050
|
||||
#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054
|
||||
#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058
|
||||
#define QSERDES_V5_TX_TX_POL_INV 0x05c
|
||||
#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
|
||||
#define QSERDES_V5_TX_BIST_PATTERN1 0x064
|
||||
#define QSERDES_V5_TX_BIST_PATTERN2 0x068
|
||||
#define QSERDES_V5_TX_BIST_PATTERN3 0x06c
|
||||
#define QSERDES_V5_TX_BIST_PATTERN4 0x070
|
||||
#define QSERDES_V5_TX_BIST_PATTERN5 0x074
|
||||
#define QSERDES_V5_TX_BIST_PATTERN6 0x078
|
||||
#define QSERDES_V5_TX_BIST_PATTERN7 0x07c
|
||||
#define QSERDES_V5_TX_BIST_PATTERN8 0x080
|
||||
#define QSERDES_V5_TX_LANE_MODE_1 0x084
|
||||
#define QSERDES_V5_TX_LANE_MODE_2 0x088
|
||||
#define QSERDES_V5_TX_LANE_MODE_3 0x08c
|
||||
#define QSERDES_V5_TX_LANE_MODE_4 0x090
|
||||
#define QSERDES_V5_TX_LANE_MODE_5 0x094
|
||||
#define QSERDES_V5_TX_ATB_SEL1 0x098
|
||||
#define QSERDES_V5_TX_ATB_SEL2 0x09c
|
||||
#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0
|
||||
#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4
|
||||
#define QSERDES_V5_TX_PRBS_SEED1 0x0a8
|
||||
#define QSERDES_V5_TX_PRBS_SEED2 0x0ac
|
||||
#define QSERDES_V5_TX_PRBS_SEED3 0x0b0
|
||||
#define QSERDES_V5_TX_PRBS_SEED4 0x0b4
|
||||
#define QSERDES_V5_TX_RESET_GEN 0x0b8
|
||||
#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc
|
||||
#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0
|
||||
#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4
|
||||
#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8
|
||||
#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc
|
||||
#define QSERDES_V5_TX_BIST_STATUS 0x0d0
|
||||
#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4
|
||||
#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8
|
||||
#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc
|
||||
#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0
|
||||
#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4
|
||||
#define QSERDES_V5_TX_PRE_EMPH 0x0e8
|
||||
#define QSERDES_V5_TX_SW_RESET 0x0ec
|
||||
#define QSERDES_V5_TX_DCC_OFFSET 0x0f0
|
||||
#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4
|
||||
#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8
|
||||
#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc
|
||||
#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100
|
||||
#define QSERDES_V5_TX_DEBUG_BUS0 0x104
|
||||
#define QSERDES_V5_TX_DEBUG_BUS1 0x108
|
||||
#define QSERDES_V5_TX_DEBUG_BUS2 0x10c
|
||||
#define QSERDES_V5_TX_DEBUG_BUS3 0x110
|
||||
#define QSERDES_V5_TX_READ_EQCODE 0x114
|
||||
#define QSERDES_V5_TX_READ_OFFSETCODE 0x118
|
||||
#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c
|
||||
#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120
|
||||
#define QSERDES_V5_TX_VGA_READ_CODE 0x124
|
||||
#define QSERDES_V5_TX_VTH_READ_CODE 0x128
|
||||
#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c
|
||||
#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_I 0x134
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_A 0x144
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150
|
||||
#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154
|
||||
#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158
|
||||
#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c
|
||||
|
||||
/* Only for QMP V5 PHY - RX registers */
|
||||
#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000
|
||||
#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004
|
||||
#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
|
||||
#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c
|
||||
#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010
|
||||
#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
|
||||
#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018
|
||||
#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
|
||||
#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020
|
||||
#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024
|
||||
#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
|
||||
#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c
|
||||
#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
|
||||
#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
|
||||
#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038
|
||||
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
|
||||
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
|
||||
#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
|
||||
#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
|
||||
#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
|
||||
#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
|
||||
#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
|
||||
#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
|
||||
#define QSERDES_V5_RX_AUX_CONTROL 0x05c
|
||||
#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
|
||||
#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
|
||||
#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
|
||||
#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c
|
||||
#define QSERDES_V5_RX_AC_JTAG_INITN 0x070
|
||||
#define QSERDES_V5_RX_AC_JTAG_LVL 0x074
|
||||
#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
|
||||
#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c
|
||||
#define QSERDES_V5_RX_RX_TERM_BW 0x080
|
||||
#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084
|
||||
#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088
|
||||
#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
|
||||
#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090
|
||||
#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
|
||||
#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098
|
||||
#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
|
||||
#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0
|
||||
#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4
|
||||
#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8
|
||||
#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac
|
||||
#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
|
||||
#define QSERDES_V5_RX_DFE_1 0x0b4
|
||||
#define QSERDES_V5_RX_DFE_2 0x0b8
|
||||
#define QSERDES_V5_RX_DFE_3 0x0bc
|
||||
#define QSERDES_V5_RX_DFE_4 0x0c0
|
||||
#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4
|
||||
#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8
|
||||
#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
|
||||
#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0
|
||||
#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
|
||||
#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
|
||||
#define QSERDES_V5_RX_GM_CAL 0x0dc
|
||||
#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0
|
||||
#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
|
||||
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
|
||||
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
|
||||
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
|
||||
#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
|
||||
#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104
|
||||
#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108
|
||||
#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c
|
||||
#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
|
||||
#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
|
||||
#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
|
||||
#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
|
||||
#define QSERDES_V5_RX_SIGDET_LVL 0x120
|
||||
#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
|
||||
#define QSERDES_V5_RX_RX_BAND 0x128
|
||||
#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c
|
||||
#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130
|
||||
#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134
|
||||
#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138
|
||||
#define QSERDES_V5_RX_SJ_AMP1 0x13c
|
||||
#define QSERDES_V5_RX_SJ_AMP2 0x140
|
||||
#define QSERDES_V5_RX_SJ_PER1 0x144
|
||||
#define QSERDES_V5_RX_SJ_PER2 0x148
|
||||
#define QSERDES_V5_RX_PPM_OFFSET1 0x14c
|
||||
#define QSERDES_V5_RX_PPM_OFFSET2 0x150
|
||||
#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154
|
||||
#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158
|
||||
#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
|
||||
#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
|
||||
#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
|
||||
#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
|
||||
#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
|
||||
#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
|
||||
#define QSERDES_V5_RX_PHPRE_CTRL 0x198
|
||||
#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c
|
||||
#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
|
||||
#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
|
||||
#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
|
||||
#define QSERDES_V5_RX_DCC_CTRL2 0x1ac
|
||||
#define QSERDES_V5_RX_VTH_CODE 0x1b0
|
||||
#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4
|
||||
#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8
|
||||
#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc
|
||||
#define QSERDES_V5_RX_PI_CTRL1 0x1c0
|
||||
#define QSERDES_V5_RX_PI_CTRL2 0x1c4
|
||||
#define QSERDES_V5_RX_PI_QUAD 0x1c8
|
||||
#define QSERDES_V5_RX_IDATA1 0x1cc
|
||||
#define QSERDES_V5_RX_IDATA2 0x1d0
|
||||
#define QSERDES_V5_RX_AUX_DATA1 0x1d4
|
||||
#define QSERDES_V5_RX_AUX_DATA2 0x1d8
|
||||
#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc
|
||||
#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0
|
||||
#define QSERDES_V5_RX_RX_SIGDET 0x1e4
|
||||
#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8
|
||||
|
||||
/* Only for QMP V5 UFS ? */
|
||||
#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
|
||||
#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
|
||||
#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
|
||||
#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,83 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_
|
||||
|
||||
#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
|
||||
#define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
|
||||
#define QSERDES_V6_TX_TX_DRV_LVL 0x14
|
||||
#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
|
||||
#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
|
||||
#define QSERDES_V6_TX_TX_BAND 0x24
|
||||
#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
|
||||
#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
|
||||
#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
|
||||
#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
|
||||
#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40
|
||||
#define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN 0x54
|
||||
#define QSERDES_V6_TX_HIGHZ_DRVR_EN 0x58
|
||||
#define QSERDES_V6_TX_TX_POL_INV 0x5c
|
||||
#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
|
||||
#define QSERDES_V6_TX_BIST_PATTERN7 0x7c
|
||||
#define QSERDES_V6_TX_LANE_MODE_1 0x84
|
||||
#define QSERDES_V6_TX_LANE_MODE_2 0x88
|
||||
#define QSERDES_V6_TX_LANE_MODE_3 0x8c
|
||||
#define QSERDES_V6_TX_LANE_MODE_4 0x90
|
||||
#define QSERDES_V6_TX_LANE_MODE_5 0x94
|
||||
#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4
|
||||
#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0
|
||||
#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4
|
||||
#define QSERDES_V6_TX_VMODE_CTRL1 0xc8
|
||||
#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4
|
||||
|
||||
#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08
|
||||
#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14
|
||||
#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30
|
||||
#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
|
||||
#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
|
||||
#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
|
||||
#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44
|
||||
#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c
|
||||
#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50
|
||||
#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54
|
||||
#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58
|
||||
#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60
|
||||
#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc
|
||||
#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4
|
||||
#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8
|
||||
#define QSERDES_V6_RX_GM_CAL 0xdc
|
||||
#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
|
||||
#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
|
||||
#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
|
||||
#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8
|
||||
#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc
|
||||
#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
|
||||
#define QSERDES_V6_RX_SIDGET_ENABLES 0x118
|
||||
#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c
|
||||
#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124
|
||||
#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c
|
||||
#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160
|
||||
#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164
|
||||
#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168
|
||||
#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c
|
||||
#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170
|
||||
#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174
|
||||
#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178
|
||||
#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c
|
||||
#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180
|
||||
#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184
|
||||
#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188
|
||||
#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c
|
||||
#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190
|
||||
#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194
|
||||
#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0
|
||||
#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
|
||||
#define QSERDES_V6_RX_DCC_CTRL1 0x1a8
|
||||
#define QSERDES_V6_RX_VTH_CODE 0x1b0
|
||||
#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4
|
||||
#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,51 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_
|
||||
|
||||
#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
|
||||
#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
|
||||
#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
|
||||
#define QSERDES_V6_20_TX_LANE_MODE_1 0x78
|
||||
#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
|
||||
#define QSERDES_V6_20_TX_LANE_MODE_3 0x80
|
||||
|
||||
#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
|
||||
#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
|
||||
#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18
|
||||
#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
|
||||
#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
|
||||
#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c
|
||||
#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0
|
||||
#define QSERDES_V6_20_RX_DFE_1 0xac
|
||||
#define QSERDES_V6_20_RX_DFE_2 0xb0
|
||||
#define QSERDES_V6_20_RX_DFE_3 0xb4
|
||||
#define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4
|
||||
#define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0
|
||||
#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8
|
||||
#define QSERDES_V6_20_RX_GM_CAL 0x10c
|
||||
#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120
|
||||
#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148
|
||||
#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188
|
||||
#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194
|
||||
#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc
|
||||
#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4
|
||||
#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8
|
||||
#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc
|
||||
#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200
|
||||
#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204
|
||||
#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208
|
||||
#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c
|
||||
#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210
|
||||
#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214
|
||||
#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218
|
||||
#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c
|
||||
#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220
|
||||
#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224
|
||||
#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228
|
||||
#define QSERDES_V6_20_RX_BKUP_CTRL1 0x22c
|
||||
|
||||
#endif
|
||||
@@ -33,8 +33,10 @@
|
||||
#include "phy-qcom-qmp-pcs-ufs-v6.h"
|
||||
|
||||
#include "phy-qcom-qmp-qserdes-com-v4.h"
|
||||
#include "phy-qcom-qmp-qserdes-com-v5.h"
|
||||
#include "phy-qcom-qmp-qserdes-com-v6.h"
|
||||
#include "phy-qcom-qmp-qserdes-txrx-v4.h"
|
||||
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
|
||||
#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
|
||||
|
||||
/* QPHY_SW_RESET bit */
|
||||
@@ -97,6 +99,13 @@ static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
|
||||
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
|
||||
};
|
||||
|
||||
static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
|
||||
[QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
|
||||
[QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
|
||||
[QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
|
||||
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
|
||||
};
|
||||
|
||||
static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
|
||||
[QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
|
||||
[QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
|
||||
@@ -458,6 +467,128 @@ static const struct qmp_ufs_init_tbl sm8650_ufsphy_rx[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_serdes[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_tx[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_rx[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_pcs[] = {
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_tx[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_rx[] = {
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
|
||||
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_pcs[] = {
|
||||
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_init_tbl sm8650_ufsphy_pcs[] = {
|
||||
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
|
||||
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
|
||||
@@ -690,6 +821,11 @@ static const char * const sdm845_ufs_phy_clk_l[] = {
|
||||
"ref", "ref_aux",
|
||||
};
|
||||
|
||||
/* the primary usb3 phy on sm8250 doesn't have a ref clock */
|
||||
static const char * const sm8450_ufs_phy_clk_l[] = {
|
||||
"qref", "ref", "ref_aux",
|
||||
};
|
||||
|
||||
/* list of regulators */
|
||||
static const char * const qmp_ufs_vreg_l[] = {
|
||||
"vdda-phy", "vdda-pll",
|
||||
@@ -909,6 +1045,40 @@ static const struct qmp_ufs_cfg sc7280_ufsphy_cfg = {
|
||||
.regs = ufsphy_v4_regs_layout,
|
||||
};
|
||||
|
||||
static const struct qmp_ufs_cfg sa8775p_ufsphy_cfg = {
|
||||
.lanes = 2,
|
||||
|
||||
.offsets = &qmp_ufs_offsets,
|
||||
|
||||
.tbls = {
|
||||
.serdes = sm8350_ufsphy_serdes,
|
||||
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
|
||||
.tx = sm8350_ufsphy_tx,
|
||||
.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
|
||||
.rx = sm8350_ufsphy_rx,
|
||||
.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
|
||||
.pcs = sm8350_ufsphy_pcs,
|
||||
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
|
||||
},
|
||||
.tbls_hs_b = {
|
||||
.serdes = sm8350_ufsphy_hs_b_serdes,
|
||||
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
|
||||
},
|
||||
.tbls_hs_g4 = {
|
||||
.tx = sm8350_ufsphy_g4_tx,
|
||||
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
|
||||
.rx = sm8350_ufsphy_g4_rx,
|
||||
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
|
||||
.pcs = sm8350_ufsphy_g4_pcs,
|
||||
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
|
||||
},
|
||||
.clk_list = sm8450_ufs_phy_clk_l,
|
||||
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
|
||||
.vreg_list = qmp_ufs_vreg_l,
|
||||
.num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
|
||||
.regs = ufsphy_v5_regs_layout,
|
||||
};
|
||||
|
||||
static void qmp_ufs_configure_lane(void __iomem *base,
|
||||
const struct qmp_ufs_init_tbl tbl[],
|
||||
int num,
|
||||
@@ -1295,6 +1465,7 @@ static struct phy_ops qmp_ufs_ops = {
|
||||
};
|
||||
|
||||
static const struct udevice_id qmp_ufs_ids[] = {
|
||||
{ .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, },
|
||||
{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
|
||||
{ .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
|
||||
{ .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },
|
||||
|
||||
@@ -83,6 +83,13 @@ config PINCTRL_QCOM_SM8650
|
||||
Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
|
||||
as well as the associated GPIO driver.
|
||||
|
||||
config PINCTRL_QCOM_X1E80100
|
||||
bool "Qualcomm X1E80100 GCC"
|
||||
select PINCTRL_QCOM
|
||||
help
|
||||
Say Y here to enable support for pinctrl on the Snapdragon X1E80100 SoC,
|
||||
as well as the associated GPIO driver.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
||||
@@ -14,3 +14,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_X1E80100) += pinctrl-x1e80100.o
|
||||
|
||||
@@ -16,6 +16,7 @@ static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
|
||||
static const struct pinctrl_function msm_pinctrl_functions[] = {
|
||||
{"qup1_se7", 1},
|
||||
{"gpio", 0},
|
||||
{"pcie1_clk_req_n", 1},
|
||||
};
|
||||
|
||||
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
|
||||
|
||||
@@ -16,6 +16,8 @@ static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
|
||||
static const struct pinctrl_function msm_pinctrl_functions[] = {
|
||||
{"qup2_se7", 1},
|
||||
{"gpio", 0},
|
||||
{"pcie0_clk_req_n", 1},
|
||||
{"pcie1_clk_req_n", 1},
|
||||
};
|
||||
|
||||
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
|
||||
|
||||
@@ -0,0 +1,105 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Qualcomm x1e80100 pinctrl
|
||||
*
|
||||
* (C) Copyright 2024 Linaro Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
|
||||
#include "pinctrl-qcom.h"
|
||||
|
||||
#define MAX_PIN_NAME_LEN 32
|
||||
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
|
||||
|
||||
static const struct pinctrl_function msm_pinctrl_functions[] = {
|
||||
{"qup2_se5", 1},
|
||||
{"pcie3_clk", 1},
|
||||
{"pcie4_clk", 1},
|
||||
{"pcie5_clk", 1},
|
||||
{"pcie6a_clk", 1},
|
||||
{"pcie6b_clk", 1},
|
||||
{"gpio", 0},
|
||||
};
|
||||
|
||||
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
|
||||
{ \
|
||||
.name = pg_name, \
|
||||
.ctl_reg = ctl, \
|
||||
.io_reg = 0, \
|
||||
.pull_bit = pull, \
|
||||
.drv_bit = drv, \
|
||||
.oe_bit = -1, \
|
||||
.in_bit = -1, \
|
||||
.out_bit = -1, \
|
||||
}
|
||||
|
||||
#define UFS_RESET(pg_name, ctl) \
|
||||
{ \
|
||||
.name = pg_name, \
|
||||
.ctl_reg = ctl, \
|
||||
.io_reg = ctl + 0x4, \
|
||||
.pull_bit = 3, \
|
||||
.drv_bit = 0, \
|
||||
.oe_bit = -1, \
|
||||
.in_bit = -1, \
|
||||
.out_bit = 0, \
|
||||
}
|
||||
|
||||
static const struct msm_special_pin_data msm_special_pins_data[] = {
|
||||
[0] = UFS_RESET("ufs_reset", 0xf9000),
|
||||
[1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xf2000, 14, 6),
|
||||
[2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xf2000, 11, 3),
|
||||
[3] = SDC_QDSD_PINGROUP("sdc2_data", 0xf2000, 9, 0),
|
||||
};
|
||||
|
||||
static const char *x1e80100_get_function_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return msm_pinctrl_functions[selector].name;
|
||||
}
|
||||
|
||||
static const char *x1e80100_get_pin_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
if (selector >= 238 && selector <= 241)
|
||||
snprintf(pin_name, MAX_PIN_NAME_LEN,
|
||||
msm_special_pins_data[selector - 238].name);
|
||||
else
|
||||
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
|
||||
|
||||
return pin_name;
|
||||
}
|
||||
|
||||
static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
|
||||
unsigned int selector)
|
||||
{
|
||||
return msm_pinctrl_functions[selector].val;
|
||||
}
|
||||
|
||||
static struct msm_pinctrl_data x1e80100_data = {
|
||||
.pin_data = {
|
||||
.pin_count = 242,
|
||||
.special_pins_start = 238,
|
||||
.special_pins_data = msm_special_pins_data,
|
||||
},
|
||||
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
|
||||
.get_function_name = x1e80100_get_function_name,
|
||||
.get_function_mux = x1e80100_get_function_mux,
|
||||
.get_pin_name = x1e80100_get_pin_name,
|
||||
};
|
||||
|
||||
static const struct udevice_id msm_pinctrl_ids[] = {
|
||||
{ .compatible = "qcom,x1e80100-tlmm", .data = (ulong)&x1e80100_data },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pinctrl_x1e80100) = {
|
||||
.name = "pinctrl_x1e80100",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = msm_pinctrl_ids,
|
||||
.ops = &msm_pinctrl_ops,
|
||||
.bind = msm_pinctrl_bind,
|
||||
};
|
||||
|
||||
@@ -536,6 +536,21 @@ static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = {
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct rpmh_vreg_init_data pmc8380_vreg_data[] = {
|
||||
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"),
|
||||
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"),
|
||||
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"),
|
||||
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_mv, "vdd-s4"),
|
||||
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"),
|
||||
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_lv, "vdd-s6"),
|
||||
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525_lv, "vdd-s7"),
|
||||
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525_lv, "vdd-s8"),
|
||||
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
|
||||
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
|
||||
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
|
||||
{}
|
||||
};
|
||||
|
||||
/* probe an individual regulator */
|
||||
static int rpmh_regulator_probe(struct udevice *dev)
|
||||
{
|
||||
@@ -662,6 +677,10 @@ static const struct udevice_id rpmh_regulator_ids[] = {
|
||||
.compatible = "qcom,pm8550vs-rpmh-regulators",
|
||||
.data = (ulong)pm8550vs_vreg_data,
|
||||
},
|
||||
{
|
||||
.compatible = "qcom,pmc8380-rpmh-regulators",
|
||||
.data = (ulong)pmc8380_vreg_data,
|
||||
},
|
||||
{ /* sentinal */ },
|
||||
};
|
||||
|
||||
|
||||
+12
-1
@@ -34,6 +34,7 @@
|
||||
struct msm_rng_priv {
|
||||
phys_addr_t base;
|
||||
struct clk clk;
|
||||
bool skip_init;
|
||||
};
|
||||
|
||||
static int msm_rng_read(struct udevice *dev, void *data, size_t len)
|
||||
@@ -100,10 +101,15 @@ static int msm_rng_probe(struct udevice *dev)
|
||||
|
||||
int ret;
|
||||
|
||||
priv->skip_init = (bool)dev_get_driver_data(dev);
|
||||
|
||||
priv->base = dev_read_addr(dev);
|
||||
if (priv->base == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
if (priv->skip_init)
|
||||
return 0;
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -119,6 +125,9 @@ static int msm_rng_remove(struct udevice *dev)
|
||||
{
|
||||
struct msm_rng_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (priv->skip_init)
|
||||
return 0;
|
||||
|
||||
return msm_rng_enable(priv, 0);
|
||||
}
|
||||
|
||||
@@ -127,7 +136,9 @@ static const struct dm_rng_ops msm_rng_ops = {
|
||||
};
|
||||
|
||||
static const struct udevice_id msm_rng_match[] = {
|
||||
{ .compatible = "qcom,prng", },
|
||||
{ .compatible = "qcom,prng", .data = (ulong)false },
|
||||
{ .compatible = "qcom,prng-ee", .data = (ulong)true },
|
||||
{ .compatible = "qcom,trng", .data = (ulong)true },
|
||||
{},
|
||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "sa8775p-ride-r3.dts"
|
||||
/ {
|
||||
model = "Qualcomm QCS9100 Ride Rev3";
|
||||
compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";
|
||||
};
|
||||
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "sa8775p-ride.dts"
|
||||
/ {
|
||||
model = "Qualcomm QCS9100 Ride";
|
||||
compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p";
|
||||
};
|
||||
@@ -390,6 +390,9 @@
|
||||
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
|
||||
#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
|
||||
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
|
||||
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
|
||||
#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
|
||||
#define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */
|
||||
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
||||
#define PCI_EXP_LNKCTL 16 /* Link Control */
|
||||
#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
|
||||
@@ -404,6 +407,7 @@
|
||||
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
||||
#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
|
||||
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
||||
#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
|
||||
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
||||
#define PCI_EXP_RTCTL 28 /* Root Control */
|
||||
#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
|
||||
|
||||
Reference in New Issue
Block a user