arm: renesas: Enable RPC on R-Car R8A78000 X5H Cortex-M33 RSIP port

Enable RPC and HyperFlash support on R-Car R8A78000 X5H Cortex-M33 RSIP.
RPC is used both to update the HF content, which includes the U-Boot on
RSIP itself and SCP firmware, as well as access the U-Boot environment
for U-Boot on RSIP.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

configs/r8a78000_ironhide_cm33_defconfig

@@ -20,6 +20,8 @@ CONFIG_BAUDRATE=1843200
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0"
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_CMD_IMI=y
 CONFIG_CMD_PSTORE=y
 CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000
@@ -29,10 +31,13 @@ CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_DM_DMA=y
 CONFIG_DM_ETH_PHY=y
+CONFIG_DM_MTD=y
 CONFIG_DM_RESET=y
 CONFIG_ENV_SIZE=0x20000
+CONFIG_FLASH_CFI_MTD=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_LAST_STAGE_INIT=y
+CONFIG_MTD_NOR_FLASH=y
 CONFIG_NET_LWIP=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NR_DRAM_BANKS=1
@@ -46,6 +51,7 @@ CONFIG_RAM_RENESAS_DBSC5=y
 CONFIG_REMOTEPROC_RENESAS_RSIP=y
 CONFIG_RENESAS_ETHER_SWITCH=y
 CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y
+CONFIG_RENESAS_RPC_HF=y
 CONFIG_SCSI=y
 CONFIG_SERIAL_PROBE_ALL=y
 CONFIG_SF_DEFAULT_SPEED=40000000
@@ -55,8 +61,14 @@ CONFIG_SYS_ARCH_TIMER=y
 CONFIG_SYS_BARGSIZE=2048
 CONFIG_SYS_BOOT_GET_CMDLINE=y
 CONFIG_SYS_CLK_FREQ=16666666
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_LOAD_ADDR=0xb8000000
 CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_TIMER_COUNTS_DOWN=y
 CONFIG_UFS=y
 CONFIG_UFS_RENESAS_GEN5=y
@@ -75,6 +87,7 @@ CONFIG_WDT_RENESAS_WWDT=y
 # CONFIG_OF_UPSTREAM is not set
 # CONFIG_BOARD_EARLY_INIT_F is not set
 # CONFIG_OF_BOARD_SETUP is not set
+# CONFIG_RENESAS_RPC_SPI is not set
 # CONFIG_SYS_ARCH_TIMER is not set
 # CONFIG_MMC is not set
 

include/configs/rcar-gen5-common.h

@@ -27,6 +27,10 @@
 #define CFG_SYS_TIMER_COUNTER		(TMU_BASE + 0xc)	/* TCNT0 */
 #define CFG_SYS_TIMER_RATE		(133333333 / 4)
 
+/* HyperFlash */
+#define CFG_SYS_FLASH_BANKS_LIST	{ 0x34000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
+
 /* Environment setting */
 #define CFG_EXTRA_ENV_SETTINGS						\
 	"rsip_ipl_params_base=0x8c100000\0"				\