ARM: dts: rockchip: rk3588: sync with Linux
Sync the devicetree with linux-next tag: next-20230525 Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Eugen Hristev
committed by
Kever Yang
Kever Yang
parent
0825522eea
commit
22a5a9724b
@@ -2,6 +2,7 @@
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "rk3588.dtsi"
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/ {
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@@ -17,6 +18,31 @@
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stdout-path = "serial2:1500000n8";
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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cooling-levels = <0 95 145 195 255>;
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fan-supply = <&vcc5v0_sys>;
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pwms = <&pwm1 0 50000 0>;
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#cooling-cells = <2>;
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};
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sound {
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compatible = "audio-graph-card";
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label = "Analog";
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widgets = "Microphone", "Mic Jack",
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"Headphone", "Headphones";
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routing = "MIC2", "Mic Jack",
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"Headphones", "HPOL",
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"Headphones", "HPOR";
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dais = <&i2s0_8ch_p0>;
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hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&hp_detect>;
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};
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vcc5v0_sys: vcc5v0-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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@@ -27,6 +53,132 @@
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};
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};
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&cpu_b0 {
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cpu-supply = <&vdd_cpu_big0_s0>;
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};
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&cpu_b1 {
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cpu-supply = <&vdd_cpu_big0_s0>;
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};
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&cpu_b2 {
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cpu-supply = <&vdd_cpu_big1_s0>;
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};
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&cpu_b3 {
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cpu-supply = <&vdd_cpu_big1_s0>;
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0m2_xfer>;
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status = "okay";
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vdd_cpu_big0_s0: regulator@42 {
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compatible = "rockchip,rk8602";
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reg = <0x42>;
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fcs,suspend-voltage-selector = <1>;
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regulator-name = "vdd_cpu_big0_s0";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <1050000>;
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regulator-ramp-delay = <2300>;
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vin-supply = <&vcc5v0_sys>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_cpu_big1_s0: regulator@43 {
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compatible = "rockchip,rk8603", "rockchip,rk8602";
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reg = <0x43>;
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fcs,suspend-voltage-selector = <1>;
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regulator-name = "vdd_cpu_big1_s0";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <550000>;
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regulator-max-microvolt = <1050000>;
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regulator-ramp-delay = <2300>;
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vin-supply = <&vcc5v0_sys>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&i2c6 {
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status = "okay";
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hym8563: rtc@51 {
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compatible = "haoyu,hym8563";
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reg = <0x51>;
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#clock-cells = <0>;
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clock-output-names = "hym8563";
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pinctrl-names = "default";
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pinctrl-0 = <&hym8563_int>;
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
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wakeup-source;
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};
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};
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&i2c7 {
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status = "okay";
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es8316: audio-codec@11 {
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compatible = "everest,es8316";
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reg = <0x11>;
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clocks = <&cru I2S0_8CH_MCLKOUT>;
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clock-names = "mclk";
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#sound-dai-cells = <0>;
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port {
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es8316_p0_0: endpoint {
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remote-endpoint = <&i2s0_8ch_p0_0>;
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};
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};
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};
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};
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&i2s0_8ch {
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_lrck
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&i2s0_mclk
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&i2s0_sclk
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&i2s0_sdi0
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&i2s0_sdo0>;
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status = "okay";
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i2s0_8ch_p0: port {
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i2s0_8ch_p0_0: endpoint {
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dai-format = "i2s";
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mclk-fs = <256>;
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remote-endpoint = <&es8316_p0_0>;
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};
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};
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};
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&pinctrl {
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hym8563 {
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hym8563_int: hym8563-int {
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rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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sound {
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hp_detect: hp-detect {
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rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pwm1 {
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status = "okay";
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};
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&sdhci {
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bus-width = <8>;
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no-sdio;
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@@ -7,6 +7,74 @@
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#include "rk3588-pinctrl.dtsi"
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/ {
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i2s8_8ch: i2s@fddc8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc8000 0x0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 22>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO0>;
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resets = <&cru SRST_M_I2S8_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s6_8ch: i2s@fddf4000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf4000 0x0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 4>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S6_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s7_8ch: i2s@fddf8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf8000 0x0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 21>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S7_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s10_8ch: i2s@fde00000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfde00000 0x0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 24>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S10_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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gmac0: ethernet@fe1b0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe1b0000 0x0 0x10000>;
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@@ -174,18 +174,6 @@
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status = "disabled";
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};
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otp: nvmem@fecc0000 {
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compatible = "rockchip,rk3588-otp";
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reg = <0x0 0xfecc0000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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cpu_id: id@7 {
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reg = <0x07 0x10>;
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};
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};
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rng: rng@fe378000 {
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compatible = "rockchip,trngv1";
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reg = <0x0 0xfe378000 0x0 0x200>;
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+229
-5
@@ -60,6 +60,8 @@
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enable-method = "psci";
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capacity-dmips-mhz = <530>;
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clocks = <&scmi_clk SCMI_CLK_CPUL>;
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assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
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assigned-clock-rates = <816000000>;
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cpu-idle-states = <&CPU_SLEEP>;
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i-cache-size = <32768>;
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i-cache-line-size = <64>;
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@@ -136,6 +138,8 @@
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&scmi_clk SCMI_CLK_CPUB01>;
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assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
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assigned-clock-rates = <816000000>;
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cpu-idle-states = <&CPU_SLEEP>;
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i-cache-size = <65536>;
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i-cache-line-size = <64>;
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@@ -174,6 +178,8 @@
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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clocks = <&scmi_clk SCMI_CLK_CPUB23>;
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assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
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assigned-clock-rates = <816000000>;
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cpu-idle-states = <&CPU_SLEEP>;
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i-cache-size = <65536>;
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i-cache-line-size = <64>;
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@@ -222,6 +228,8 @@
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cache-size = <131072>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -230,6 +238,8 @@
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cache-size = <131072>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -238,6 +248,8 @@
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cache-size = <131072>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -246,6 +258,8 @@
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cache-size = <131072>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -254,6 +268,8 @@
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cache-size = <524288>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -262,6 +278,8 @@
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cache-size = <524288>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -270,6 +288,8 @@
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cache-size = <524288>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -278,6 +298,8 @@
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cache-size = <524288>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_cache>;
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};
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@@ -286,6 +308,8 @@
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cache-size = <3145728>;
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cache-line-size = <64>;
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cache-sets = <4096>;
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cache-level = <3>;
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cache-unified;
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};
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};
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@@ -304,10 +328,6 @@
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scmi_clk: protocol@14 {
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reg = <0x14>;
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assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
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<&scmi_clk SCMI_CLK_CPUB23>;
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assigned-clock-rates = <1200000000>,
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<1200000000>;
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#clock-cells = <1>;
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};
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@@ -414,7 +434,7 @@
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<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
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<&cru CLK_GPU>;
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assigned-clock-rates =
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<100000000>, <786432000>,
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<1100000000>, <786432000>,
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<850000000>, <1188000000>,
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<702000000>,
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<400000000>, <500000000>,
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@@ -1132,6 +1152,103 @@
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status = "disabled";
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};
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i2s0_8ch: i2s@fe470000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfe470000 0x0 0x1000>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
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dmas = <&dmac0 0>, <&dmac0 1>;
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dma-names = "tx", "rx";
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power-domains = <&power RK3588_PD_AUDIO>;
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resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
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reset-names = "tx-m", "rx-m";
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rockchip,trcm-sync-tx-only;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_lrck
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&i2s0_sclk
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&i2s0_sdi0
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&i2s0_sdi1
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&i2s0_sdi2
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&i2s0_sdi3
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&i2s0_sdo0
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&i2s0_sdo1
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&i2s0_sdo2
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&i2s0_sdo3>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s1_8ch: i2s@fe480000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfe480000 0x0 0x1000>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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dmas = <&dmac0 2>, <&dmac0 3>;
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dma-names = "tx", "rx";
|
||||
resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
||||
reset-names = "tx-m", "rx-m";
|
||||
rockchip,trcm-sync-tx-only;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1m0_lrck
|
||||
&i2s1m0_sclk
|
||||
&i2s1m0_sdi0
|
||||
&i2s1m0_sdi1
|
||||
&i2s1m0_sdi2
|
||||
&i2s1m0_sdi3
|
||||
&i2s1m0_sdo0
|
||||
&i2s1m0_sdo1
|
||||
&i2s1m0_sdo2
|
||||
&i2s1m0_sdo3>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s2_2ch: i2s@fe490000 {
|
||||
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x0 0xfe490000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac1 0>, <&dmac1 1>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3588_PD_AUDIO>;
|
||||
rockchip,trcm-sync-tx-only;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s2m1_lrck
|
||||
&i2s2m1_sclk
|
||||
&i2s2m1_sdi
|
||||
&i2s2m1_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s3_2ch: i2s@fe4a0000 {
|
||||
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x0 0xfe4a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac1 2>, <&dmac1 3>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3588_PD_AUDIO>;
|
||||
rockchip,trcm-sync-tx-only;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s3_lrck
|
||||
&i2s3_sclk
|
||||
&i2s3_sdi
|
||||
&i2s3_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@fe600000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
|
||||
@@ -1141,7 +1258,24 @@
|
||||
mbi-alias = <0x0 0xfe610000>;
|
||||
mbi-ranges = <424 56>;
|
||||
msi-controller;
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#interrupt-cells = <4>;
|
||||
#size-cells = <2>;
|
||||
|
||||
its0: msi-controller@fe640000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x0 0xfe640000 0x0 0x20000>;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
its1: msi-controller@fe660000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x0 0xfe660000 0x0 0x20000>;
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
ppi-partitions {
|
||||
ppi_partition0: interrupt-partition-0 {
|
||||
@@ -1241,6 +1375,22 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer0: timer@feae0000 {
|
||||
compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
|
||||
reg = <0x0 0xfeae0000 0x0 0x20>;
|
||||
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
|
||||
clock-names = "pclk", "timer";
|
||||
};
|
||||
|
||||
wdt: watchdog@feaf0000 {
|
||||
compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
|
||||
reg = <0x0 0xfeaf0000 0x0 0x100>;
|
||||
clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
|
||||
clock-names = "tclk", "pclk";
|
||||
interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
};
|
||||
|
||||
spi0: spi@feb00000 {
|
||||
compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
||||
reg = <0x0 0xfeb00000 0x0 0x1000>;
|
||||
@@ -1572,6 +1722,26 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsadc: tsadc@fec00000 {
|
||||
compatible = "rockchip,rk3588-tsadc";
|
||||
reg = <0x0 0xfec00000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "tsadc", "apb_pclk";
|
||||
assigned-clocks = <&cru CLK_TSADC>;
|
||||
assigned-clock-rates = <2000000>;
|
||||
resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
|
||||
reset-names = "tsadc-apb", "tsadc";
|
||||
rockchip,hw-tshut-temp = <120000>;
|
||||
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
pinctrl-0 = <&tsadc_gpio_func>;
|
||||
pinctrl-1 = <&tsadc_shut>;
|
||||
pinctrl-names = "gpio", "otpout";
|
||||
#thermal-sensor-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@fec80000 {
|
||||
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfec80000 0x0 0x1000>;
|
||||
@@ -1627,6 +1797,60 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
otp: efuse@fecc0000 {
|
||||
compatible = "rockchip,rk3588-otp";
|
||||
reg = <0x0 0xfecc0000 0x0 0x400>;
|
||||
clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
|
||||
<&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
|
||||
clock-names = "otp", "apb_pclk", "phy", "arb";
|
||||
resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
|
||||
<&cru SRST_OTPC_ARB>;
|
||||
reset-names = "otp", "apb", "arb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpu_code: cpu-code@2 {
|
||||
reg = <0x02 0x2>;
|
||||
};
|
||||
|
||||
otp_id: id@7 {
|
||||
reg = <0x07 0x10>;
|
||||
};
|
||||
|
||||
cpub0_leakage: cpu-leakage@17 {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
|
||||
cpub1_leakage: cpu-leakage@18 {
|
||||
reg = <0x18 0x1>;
|
||||
};
|
||||
|
||||
cpul_leakage: cpu-leakage@19 {
|
||||
reg = <0x19 0x1>;
|
||||
};
|
||||
|
||||
log_leakage: log-leakage@1a {
|
||||
reg = <0x1a 0x1>;
|
||||
};
|
||||
|
||||
gpu_leakage: gpu-leakage@1b {
|
||||
reg = <0x1b 0x1>;
|
||||
};
|
||||
|
||||
otp_cpu_version: cpu-version@1c {
|
||||
reg = <0x1c 0x1>;
|
||||
bits = <3 3>;
|
||||
};
|
||||
|
||||
npu_leakage: npu-leakage@28 {
|
||||
reg = <0x28 0x1>;
|
||||
};
|
||||
|
||||
codec_leakage: codec-leakage@29 {
|
||||
reg = <0x29 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
dmac2: dma-controller@fed10000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xfed10000 0x0 0x4000>;
|
||||
|
||||
Reference in New Issue
Block a user