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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

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Two fixes for R-Car Gen5 RSIP, one to surely build u-boot-elf.shdr and
one to make u-boot-elf.shdr compatible with tooling.

Two fixes for R-Car Gen4, which could hang in SPL without them.
This commit is contained in:
Tom Rini
2026-06-14 15:35:00 -06:00
parent 5ca1a73c7d cc5d760ace
commit 1e80ee4144
4 changed files with 25 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Kconfig
+2 -1
View File
@@ -548,7 +548,8 @@ config REMAKE_ELF
config BUILD_TARGET
string "Build target special images"
default "u-boot-elf.srec" if RCAR_64
default "u-boot-elf.shdr" if RCAR_64 && RCAR_64_RSIP
default "u-boot-elf.srec" if RCAR_64 && !RCAR_64_RSIP
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL
arch/arm/mach-renesas/Kconfig.rcar4
+3
View File
@@ -11,12 +11,14 @@ config R8A779A0
config R8A779F0
bool "Renesas SoC R8A779F0"
select GICV3
select GICV3_SUPPORT_GIC600
imply CLK_R8A779F0
imply PINCTRL_PFC_R8A779F0
config R8A779G0
bool "Renesas SoC R8A779G0"
select GICV3
select GICV3_SUPPORT_GIC600
select BINMAN
select SUPPORT_SPL
imply SPL
@@ -33,6 +35,7 @@ config R8A779G0
config R8A779H0
bool "Renesas SoC R8A779H0"
select GICV3
select GICV3_SUPPORT_GIC600
imply CLK_R8A779H0
imply PINCTRL_PFC_R8A779H0
arch/arm/mach-renesas/Makefile
+2
View File
@@ -50,6 +50,8 @@ quiet_cmd_srec_cat = SRECCAT $@
quiet_cmd_srec_shdr_cat = SRECCAT $@
cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \
-Output_Block_Size 16 \
-DISable Data_Count \
-Execution_Start_Address 0x18400000 \
-generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \
-generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \
-generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \
board/renesas/common/gen4-spl.c
+18 -23
View File
@@ -18,6 +18,12 @@
#include <mapmem.h>
#include <spl.h>
#define APMU_BASE 0xe6170000U
#define CL0GRP3_BIT BIT(3)
#define CL1GRP3_BIT BIT(7)
#define RTGRP3_BIT BIT(19)
#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
#define CNTCR_EN BIT(0)
#ifdef CONFIG_SPL_BUILD
@@ -47,6 +53,18 @@ void board_init_f(ulong dummy)
struct udevice *dev;
int ret;
/* Unlock CPG access */
writel(0x5A5AFFFF, CPGWPR);
writel(0xA5A50000, CPGWPCR);
init_generic_timer();
/* Define for Work Around of APMU */
writel(0x00ff00ff, APMU_BASE + 0x10);
writel(0x00ff00ff, APMU_BASE + 0x14);
writel(0x00ff00ff, APMU_BASE + 0x18);
writel(0x00ff00ff, APMU_BASE + 0x1c);
clrbits_le32(APMU_BASE + 0x68, BIT(29));
if (CONFIG_IS_ENABLED(OF_CONTROL)) {
ret = spl_early_init();
if (ret) {
@@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0);
}
#define APMU_BASE 0xe6170000U
#define CL0GRP3_BIT BIT(3)
#define CL1GRP3_BIT BIT(7)
#define RTGRP3_BIT BIT(19)
#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
int mach_cpu_init(void)
{
/* Unlock CPG access */
writel(0x5A5AFFFF, CPGWPR);
writel(0xA5A50000, CPGWPCR);
init_generic_timer();
/* Define for Work Around of APMU */
writel(0x00ff00ff, APMU_BASE + 0x10);
writel(0x00ff00ff, APMU_BASE + 0x14);
writel(0x00ff00ff, APMU_BASE + 0x18);
writel(0x00ff00ff, APMU_BASE + 0x1c);
clrbits_le32(APMU_BASE + 0x68, BIT(29));
return 0;
}
void reset_cpu(void)
{
}