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Merge patch series "j721s2: j784s4: Add workaround for errata i2437"

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Udit Kumar <u-kumar1@ti.com> says:

Add a necessary hardware errata workaround for J721S2 and J784S4.

Bootlogs
https://gist.github.com/uditkumarti/da2a489a78d3241ecd2791c9df1c1317

Link: https://lore.kernel.org/r/20260415152152.3048491-1-u-kumar1@ti.com
This commit is contained in:
Tom Rini
2026-05-11 12:33:52 -06:00
parent 02ef1859b4 c5c3b27873
commit 1d8526fa7c
3 changed files with 88 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/mach-k3/include/mach/hardware.h
+10
View File
@@ -126,4 +126,14 @@ struct rom_extended_boot_data {
u32 get_boot_device(void);
const char *get_reset_reason(void);
#define writel_verify(val, addr) \
do { \
u32 readback; \
writel(val, addr); \
readback = readl(addr); \
if (readback != val) \
printf("writel_verify failed: addr=0x%p, expected=0x%x, got=0x%x\n", \
(void *)(addr), (val), readback); \
} while (0)
#endif /* _ASM_ARCH_HARDWARE_H_ */
arch/arm/mach-k3/j721s2/j721s2_init.c
+39
View File
@@ -40,6 +40,15 @@
#define NB_THREADMAP_BIT1 BIT(1)
#define NB_THREADMAP_BIT2 BIT(2)
/*
* RAT mapping for errata ID: i2437
*/
#define RAT_ERRATA_2437_BASE_REGION0 0x40f90000
#define RAT_ERRATA_2437_IN_ADDR 0xc0000000
#define RAT_ERRATA_2437_OUT_ADDR_U 0x0000004d
#define RAT_ERRATA_2437_OUT_ADDR_L 0x21000000
#define RAT_ERRATA_2437_CTRL 0x80000010
struct fwl_data cbass_hc_cfg0_fwls[] = {
{ "PCIE0_CFG", 2577, 7 },
{ "EMMC8SS0_CFG", 2579, 4 },
@@ -346,6 +355,36 @@ void board_init_f(ulong dummy)
if (ret)
printf("AVS init failed: %d\n", ret);
}
if (IS_ENABLED(CONFIG_CPU_V7R)) {
/*
* Errata ID i2437: SE Clock-Gating Turning Off Too Early
*
* A hardware bug is present in the C7120 Streaming Engine top level
* clock gating logic that can lead to the C7120 CPU hanging.
* Workaround: The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the
* COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the
* name of the specific C7120 core) must be enabled before power-up
* of the C7120 core to override all clock-gating.
*/
/* Setup RAT mapping */
debug("Errata i2437: Use RAT for COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register\n");
writel_verify(RAT_ERRATA_2437_IN_ADDR, RAT_ERRATA_2437_BASE_REGION0 + 0x24);
writel_verify(RAT_ERRATA_2437_OUT_ADDR_L, RAT_ERRATA_2437_BASE_REGION0 + 0x28);
writel_verify(RAT_ERRATA_2437_OUT_ADDR_U, RAT_ERRATA_2437_BASE_REGION0 + 0x2c);
writel_verify(RAT_ERRATA_2437_CTRL, RAT_ERRATA_2437_BASE_REGION0 + 0x20);
/* Enable DSP_X_DEBUG_CLKEN_OVERRIDE for C71x cores */
writel_verify(0x300, RAT_ERRATA_2437_IN_ADDR + 0x200);
/* Clear RAT mapping */
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x20);
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x24);
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x28);
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x2c);
}
}
#endif
arch/arm/mach-k3/j784s4/j784s4_init.c
+39
View File
@@ -45,6 +45,15 @@
#define NB_THREADMAP_BIT1 BIT(1)
#define NB_THREADMAP_BIT2 BIT(2)
/*
* RAT mapping for errata ID: i2437
*/
#define RAT_ERRATA_2437_BASE_REGION0 0x40f90000
#define RAT_ERRATA_2437_IN_ADDR 0xc0000000
#define RAT_ERRATA_2437_OUT_ADDR_U 0x0000004d
#define RAT_ERRATA_2437_OUT_ADDR_L 0x21000000
#define RAT_ERRATA_2437_CTRL 0x80000010
struct fwl_data infra_cbass0_fwls[] = {
{ "PSC0", 5, 1 },
{ "PLL_CTRL0", 6, 1 },
@@ -322,6 +331,36 @@ void board_init_f(ulong dummy)
setup_navss_nb();
setup_qos();
if (IS_ENABLED(CONFIG_CPU_V7R)) {
/*
* Errata ID i2437 SE Clock-Gating Turning Off Too Early
*
* A hardware bug is present in the C7120 Streaming Engine top level
* clock gating logic that can lead to the C7120 CPU hanging.
* Workaround: The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the
* COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the
* name of the specific C7120 core) must be enabled before power-up
* of the C7120 core to override all clock-gating.
*/
/* Setup RAT mapping */
debug("Errata i2437: Use RAT for COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register\n");
writel_verify(RAT_ERRATA_2437_IN_ADDR, RAT_ERRATA_2437_BASE_REGION0 + 0x24);
writel_verify(RAT_ERRATA_2437_OUT_ADDR_L, RAT_ERRATA_2437_BASE_REGION0 + 0x28);
writel_verify(RAT_ERRATA_2437_OUT_ADDR_U, RAT_ERRATA_2437_BASE_REGION0 + 0x2c);
writel_verify(RAT_ERRATA_2437_CTRL, RAT_ERRATA_2437_BASE_REGION0 + 0x20);
/* Enable DSP_X_DEBUG_CLKEN_OVERRIDE for C71x cores */
writel_verify(0xF00, RAT_ERRATA_2437_IN_ADDR + 0x200);
/* Clear RAT mapping */
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x20);
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x24);
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x28);
writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x2c);
}
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)