arm: dts: k3-am65: remove unsused am65x SoC fdt files
With all boards using TI's AM65x having enabled CONFIG_OF_UPSTREAM cleanup the unused SoC fdt files. Signed-off-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Bryan Brattlof
Tom Rini
File diff suppressed because it is too large
Load Diff
@@ -1,440 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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mcu_conf: scm-conf@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4040 0x4>;
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#phy-cells = <1>;
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};
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};
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/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
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mcu_timerio_input: pinctrl@40f04200 {
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compatible = "pinctrl-single";
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reg = <0x0 0x40f04200 0x0 0x10>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x00000101>;
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};
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/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
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mcu_timerio_output: pinctrl@40f04280 {
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compatible = "pinctrl-single";
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reg = <0x0 0x40f04280 0x0 0x8>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x00000003>;
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x80000>;
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ranges = <0x0 0x00 0x41c00000 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b00000 0x0 0x100>;
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interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 114 1>;
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcu_spi0: spi@40300000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x40300000 0x0 0x400>;
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interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 142 1>;
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power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mcu_spi1: spi@40310000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x40310000 0x0 0x400>;
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interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 143 1>;
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power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mcu_spi2: spi@40320000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x40320000 0x0 0x400>;
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interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 144 1>;
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power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tscadc0: tscadc@40200000 {
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compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
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reg = <0x0 0x40200000 0x0 0x1000>;
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interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 0 2>;
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assigned-clocks = <&k3_clks 0 2>;
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assigned-clock-rates = <60000000>;
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clock-names = "fck";
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dmas = <&mcu_udmap 0x7100>,
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<&mcu_udmap 0x7101 >;
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dma-names = "fifo0", "fifo1";
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status = "disabled";
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adc {
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#io-channel-cells = <1>;
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compatible = "ti,am654-adc", "ti,am3359-adc";
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};
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};
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tscadc1: tscadc@40210000 {
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compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
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reg = <0x0 0x40210000 0x0 0x1000>;
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interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 1 2>;
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assigned-clocks = <&k3_clks 1 2>;
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assigned-clock-rates = <60000000>;
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clock-names = "fck";
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dmas = <&mcu_udmap 0x7102>,
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<&mcu_udmap 0x7103>;
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dma-names = "fifo0", "fifo1";
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status = "disabled";
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adc {
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#io-channel-cells = <1>;
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compatible = "ti,am654-adc", "ti,am3359-adc";
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};
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};
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/*
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* The MCU domain timer interrupts are routed only to the ESM module,
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* and not currently available for Linux. The MCU domain timers are
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* of limited use without interrupts, and likely reserved by the ESM.
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*/
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mcu_timer0: timer@40400000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40400000 0x00 0x400>;
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clocks = <&k3_clks 35 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer1: timer@40410000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40410000 0x00 0x400>;
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clocks = <&k3_clks 36 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer2: timer@40420000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40420000 0x00 0x400>;
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clocks = <&k3_clks 37 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_timer3: timer@40430000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40430000 0x00 0x400>;
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clocks = <&k3_clks 38 0>;
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clock-names = "fck";
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power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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status = "reserved";
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};
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mcu_navss: bus@28380000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
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dma-coherent;
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dma-ranges;
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ti,sci-dev-id = <119>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>,
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<0x0 0x28440000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg",
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"proxy_target", "cfg";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <195>;
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msi-parent = <&inta_main_udmass>;
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};
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mcu_udmap: dma-controller@285c0000 {
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compatible = "ti,am654-navss-mcu-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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msi-parent = <&inta_main_udmass>;
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#dma-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <194>;
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ti,ringacc = <&mcu_ringacc>;
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ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
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<0xd>; /* TX_CHAN */
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ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
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<0xa>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
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};
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};
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secure_proxy_mcu: mailbox@2a480000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x0 0x2a480000 0x0 0x80000>,
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<0x0 0x2a380000 0x0 0x80000>,
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<0x0 0x2a400000 0x0 0x80000>;
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/*
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* Marked Disabled:
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* Node is incomplete as it is meant for bootloaders and
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* firmware on non-MPU processors
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*/
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status = "disabled";
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};
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m_can0: can@40528000 {
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compatible = "bosch,m_can";
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reg = <0x0 0x40528000 0x0 0x400>,
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<0x0 0x40500000 0x0 0x4400>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
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clock-names = "hclk", "cclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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m_can1: can@40568000 {
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compatible = "bosch,m_can";
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reg = <0x0 0x40568000 0x0 0x400>,
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<0x0 0x40540000 0x0 0x4400>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
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clock-names = "hclk", "cclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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fss: bus@47000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ospi0: spi@47040000 {
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compatible = "ti,am654-ospi", "cdns,qspi-nor";
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x5 0x00000000 0x1 0x0000000>;
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interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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clocks = <&k3_clks 248 0>;
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assigned-clocks = <&k3_clks 248 0>;
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assigned-clock-parents = <&k3_clks 248 2>;
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assigned-clock-rates = <166666666>;
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power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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ospi1: spi@47050000 {
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compatible = "ti,am654-ospi", "cdns,qspi-nor";
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reg = <0x0 0x47050000 0x0 0x100>,
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<0x7 0x00000000 0x1 0x00000000>;
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interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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clocks = <&k3_clks 249 6>;
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power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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mcu_cpsw: ethernet@46000000 {
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compatible = "ti,am654-cpsw-nuss";
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x46000000 0x0 0x200000>;
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reg-names = "cpsw_nuss";
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ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
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dma-coherent;
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clocks = <&k3_clks 5 10>;
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clock-names = "fck";
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power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
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dmas = <&mcu_udmap 0xf000>,
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<&mcu_udmap 0xf001>,
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<&mcu_udmap 0xf002>,
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<&mcu_udmap 0xf003>,
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<&mcu_udmap 0xf004>,
|
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<&mcu_udmap 0xf005>,
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<&mcu_udmap 0xf006>,
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<&mcu_udmap 0xf007>,
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<&mcu_udmap 0x7000>;
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dma-names = "tx0", "tx1", "tx2", "tx3",
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"tx4", "tx5", "tx6", "tx7",
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"rx";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw_port1: port@1 {
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reg = <1>;
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ti,mac-only;
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label = "port1";
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ti,syscon-efuse = <&mcu_conf 0x200>;
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phys = <&phy_gmii_sel 1>;
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};
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};
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davinci_mdio: mdio@f00 {
|
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
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reg = <0x0 0xf00 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 5 10>;
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clock-names = "fck";
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bus_freq = <1000000>;
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status = "disabled";
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||||
};
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cpts@3d000 {
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compatible = "ti,am65-cpts";
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reg = <0x0 0x3d000 0x0 0x400>;
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clocks = <&mcu_cpsw_cpts_mux>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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mcu_cpsw_cpts_mux: refclk-mux {
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#clock-cells = <0>;
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clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
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<&k3_clks 118 6>, <&k3_clks 118 3>,
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<&k3_clks 118 8>, <&k3_clks 118 14>,
|
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<&k3_clks 120 3>, <&k3_clks 121 3>;
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assigned-clocks = <&mcu_cpsw_cpts_mux>;
|
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assigned-clock-parents = <&k3_clks 118 5>;
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};
|
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};
|
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};
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mcu_r5fss0: r5fss@41000000 {
|
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compatible = "ti,am654-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
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ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
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power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,am654-r5f";
|
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reg = <0x41000000 0x00008000>,
|
||||
<0x41010000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <159>;
|
||||
ti,sci-proc-ids = <0x01 0xff>;
|
||||
resets = <&k3_reset 159 1>;
|
||||
firmware-name = "am65x-mcu-r5f0_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
compatible = "ti,am654-r5f";
|
||||
reg = <0x41400000 0x00008000>,
|
||||
<0x41410000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <245>;
|
||||
ti,sci-proc-ids = <0x02 0xff>;
|
||||
resets = <&k3_reset 245 1>;
|
||||
firmware-name = "am65x-mcu-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_rti1: watchdog@40610000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x0 0x40610000 0x0 0x100>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
|
||||
assigned-clocks = <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 135 4>;
|
||||
};
|
||||
};
|
||||
@@ -1,105 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
dmsc: system-controller@44083000 {
|
||||
compatible = "ti,am654-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
mbox-names = "rx", "tx";
|
||||
|
||||
mboxes = <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x44083000 0x1000>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x43000014 0x4>;
|
||||
};
|
||||
|
||||
wkup_pmx0: pinctrl@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x4301c000 0x118>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x42300000 0x100>;
|
||||
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@42120000 {
|
||||
compatible = "ti,am654-i2c", "ti,omap4-i2c";
|
||||
reg = <0x42120000 0x100>;
|
||||
interrupts = <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 115 1>;
|
||||
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intr_wkup_gpio: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x42200000 0x200>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <156>;
|
||||
ti,interrupt-ranges = <0 712 16>;
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@42110000 {
|
||||
compatible = "ti,am654-gpio", "ti,keystone-gpio";
|
||||
reg = <0x42110000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_wkup_gpio>;
|
||||
interrupts = <60>, <61>, <62>, <63>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <56>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
clocks = <&k3_clks 59 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
wkup_vtm0: temperature-sensor@42050000 {
|
||||
compatible = "ti,am654-vtm";
|
||||
reg = <0x42050000 0x25c>;
|
||||
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
@@ -1,110 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM6 SoC Family
|
||||
*
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM654 SoC";
|
||||
compatible = "ti,am654";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
||||
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
||||
/* MCUSS Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
|
||||
|
||||
cbass_mcu: bus@28380000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
|
||||
|
||||
cbass_wakeup: bus@42040000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* WKUP Basic peripherals */
|
||||
ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am65-main.dtsi"
|
||||
#include "k3-am65-mcu.dtsi"
|
||||
#include "k3-am65-wakeup.dtsi"
|
||||
@@ -1,45 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
mpu0_thermal: mpu0-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
thermal-sensors = <&wkup_vtm0 0>;
|
||||
|
||||
trips {
|
||||
mpu0_crit: mpu0-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mpu1_thermal: mpu1-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
thermal-sensors = <&wkup_vtm0 1>;
|
||||
|
||||
trips {
|
||||
mpu1_crit: mpu1-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mcu_thermal: mcu-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
thermal-sensors = <&wkup_vtm0 2>;
|
||||
|
||||
trips {
|
||||
mcu_crit: mcu-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,122 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM6 SoC family in Quad core configuration
|
||||
*
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am65.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1: cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
L2_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
#include "k3-am654-industrial-thermal.dtsi"
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user