imx7ulp: Switch to OF_UPSTREAM
Migrate i.MX7ULP boards to use OF_UPSTREAM feature, which allows U-Boot to directly use device trees from the Linux kernel upstream. Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Alice Guo
Fabio Estevam
@@ -1,79 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2019 NXP
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/dts-v1/;
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#include "imx7ulp.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Embedded Artists i.MX7ULP COM";
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compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
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chosen {
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stdout-path = &lpuart4;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x4000000>;
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};
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};
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&lpuart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart4>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usdhc0 {
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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non-removable;
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bus-width = <8>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
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IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
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IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
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IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
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>;
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};
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};
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@@ -1,133 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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/dts-v1/;
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#include "imx7ulp.dtsi"
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/ {
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model = "NXP i.MX7ULP EVK";
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compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
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chosen {
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stdout-path = &lpuart4;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&tpm4 1 50000 0>;
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brightness-levels = <0 20 25 30 35 40 100>;
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default-brightness-level = <6>;
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status = "okay";
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};
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reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_vbus>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_vsd_3v3: regulator-vsd-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0_rst>;
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gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&lpuart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart4>;
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status = "okay";
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};
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&tpm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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disable-over-current;
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status = "okay";
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};
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&usdhc0 {
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_vsd_3v3>;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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bias-pull-up;
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};
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pinctrl_pwm0: pwm0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
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>;
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};
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pinctrl_usbotg1_vbus: otg1vbusgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC0__PTC0 0x20000
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
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>;
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};
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pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD0__PTD0 0x3
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>;
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};
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};
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@@ -1,461 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx7ulp-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "imx7ulp-pinfunc.h"
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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gpio0 = &gpio_ptc;
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gpio1 = &gpio_ptd;
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gpio2 = &gpio_pte;
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gpio3 = &gpio_ptf;
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i2c0 = &lpi2c6;
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i2c1 = &lpi2c7;
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mmc0 = &usdhc0;
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mmc1 = &usdhc1;
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serial0 = &lpuart4;
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serial1 = &lpuart5;
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serial2 = &lpuart6;
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serial3 = &lpuart7;
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usbphy0 = &usbphy1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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};
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};
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intc: interrupt-controller@40021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x40021000 0x1000>,
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<0x40022000 0x1000>;
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};
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rosc: clock-rosc {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "rosc";
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#clock-cells = <0>;
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};
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sosc: clock-sosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "sosc";
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#clock-cells = <0>;
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};
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sirc: clock-sirc {
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-output-names = "sirc";
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#clock-cells = <0>;
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};
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firc: clock-firc {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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clock-output-names = "firc";
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#clock-cells = <0>;
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};
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upll: clock-upll {
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compatible = "fixed-clock";
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clock-frequency = <480000000>;
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clock-output-names = "upll";
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#clock-cells = <0>;
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};
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ahbbridge0: bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40000000 0x800000>;
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ranges;
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edma1: dma-controller@40080000 {
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#dma-cells = <2>;
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compatible = "fsl,imx7ulp-edma";
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reg = <0x40080000 0x2000>,
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<0x40210000 0x1000>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dma", "dmamux0";
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clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
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<&pcc2 IMX7ULP_CLK_DMA_MUX1>;
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};
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crypto: crypto@40240000 {
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compatible = "fsl,sec-v4.0";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40240000 0x10000>;
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ranges = <0 0x40240000 0x10000>;
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clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
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<&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
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clock-names = "aclk", "ipg";
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sec_jr0: jr@1000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr@2000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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lpuart4: serial@402d0000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x402d0000 0x1000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
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clock-names = "ipg";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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assigned-clock-rates = <24000000>;
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status = "disabled";
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};
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lpuart5: serial@402e0000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x402e0000 0x1000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
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clock-names = "ipg";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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tpm4: pwm@40250000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x40250000 0x1000>;
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assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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tpm5: tpm@40260000 {
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compatible = "fsl,imx7ulp-tpm";
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reg = <0x40260000 0x1000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&pcc2 IMX7ULP_CLK_LPTPM5>;
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clock-names = "ipg", "per";
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};
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usbotg1: usb@40330000 {
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compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
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reg = <0x40330000 0x200>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc2 IMX7ULP_CLK_USB0>;
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phys = <&usbphy1>;
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fsl,usbmisc = <&usbmisc1 0>;
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x8>;
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rx-burst-size-dword = <0x8>;
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status = "disabled";
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};
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usbmisc1: usbmisc@40330200 {
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compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
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#index-cells = <1>;
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reg = <0x40330200 0x200>;
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};
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usbphy1: usb-phy@40350000 {
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compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
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reg = <0x40350000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
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#phy-cells = <0>;
|
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};
|
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usdhc0: mmc@40370000 {
|
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compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
|
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reg = <0x40370000 0x10000>;
|
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC0>;
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clock-names = "ipg", "ahb", "per";
|
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bus-width = <4>;
|
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fsl,tuning-start-tap = <20>;
|
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fsl,tuning-step = <2>;
|
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status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: mmc@40380000 {
|
||||
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
|
||||
reg = <0x40380000 0x10000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scg1: clock-controller@403e0000 {
|
||||
compatible = "fsl,imx7ulp-scg1";
|
||||
reg = <0x403e0000 0x10000>;
|
||||
clocks = <&rosc>, <&sosc>, <&sirc>,
|
||||
<&firc>, <&upll>;
|
||||
clock-names = "rosc", "sosc", "sirc",
|
||||
"firc", "upll";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@403d0000 {
|
||||
compatible = "fsl,imx7ulp-wdt";
|
||||
reg = <0x403d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
|
||||
timeout-sec = <40>;
|
||||
};
|
||||
|
||||
pcc2: clock-controller@403f0000 {
|
||||
compatible = "fsl,imx7ulp-pcc2";
|
||||
reg = <0x403f0000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_DDR_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
||||
<&scg1 IMX7ULP_CLK_UPLL>,
|
||||
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_ROSC>,
|
||||
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
||||
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
||||
"apll_pfd2", "apll_pfd1", "apll_pfd0",
|
||||
"upll", "sosc_bus_clk",
|
||||
"firc_bus_clk", "rosc", "spll_bus_clk";
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
||||
};
|
||||
|
||||
smc1: clock-controller@40410000 {
|
||||
compatible = "fsl,imx7ulp-smc1";
|
||||
reg = <0x40410000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
|
||||
clock-names = "divcore", "hsrun_divcore";
|
||||
};
|
||||
|
||||
pcc3: clock-controller@40b30000 {
|
||||
compatible = "fsl,imx7ulp-pcc3";
|
||||
reg = <0x40b30000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_DDR_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
||||
<&scg1 IMX7ULP_CLK_UPLL>,
|
||||
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_ROSC>,
|
||||
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
||||
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
||||
"apll_pfd2", "apll_pfd1", "apll_pfd0",
|
||||
"upll", "sosc_bus_clk",
|
||||
"firc_bus_clk", "rosc", "spll_bus_clk";
|
||||
};
|
||||
};
|
||||
|
||||
ahbbridge1: bus@40800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40800000 0x800000>;
|
||||
ranges;
|
||||
|
||||
lpi2c6: i2c@40a40000 {
|
||||
compatible = "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x40a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c7: i2c@40a50000 {
|
||||
compatible = "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x40a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart6: serial@40a60000 {
|
||||
compatible = "fsl,imx7ulp-lpuart";
|
||||
reg = <0x40a60000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart7: serial@40a70000 {
|
||||
compatible = "fsl,imx7ulp-lpuart";
|
||||
reg = <0x40a70000 0x1000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
memory-controller@40ab0000 {
|
||||
compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
|
||||
reg = <0x40ab0000 0x1000>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
|
||||
};
|
||||
|
||||
iomuxc1: pinctrl@40ac0000 {
|
||||
compatible = "fsl,imx7ulp-iomuxc1";
|
||||
reg = <0x40ac0000 0x1000>;
|
||||
};
|
||||
|
||||
gpio_ptc: gpio@40ae0000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLC>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 0 20>;
|
||||
};
|
||||
|
||||
gpio_ptd: gpio@40af0000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40af0000 0x1000 0x400f0040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLD>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 32 12>;
|
||||
};
|
||||
|
||||
gpio_pte: gpio@40b00000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40b00000 0x1000 0x400f0080 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 64 16>;
|
||||
};
|
||||
|
||||
gpio_ptf: gpio@40b10000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLF>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 96 20>;
|
||||
};
|
||||
};
|
||||
|
||||
m4aips1: bus@41080000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x41080000 0x80000>;
|
||||
ranges;
|
||||
|
||||
sim: sim@410a3000 {
|
||||
compatible = "fsl,imx7ulp-sim", "syscon";
|
||||
reg = <0x410a3000 0x1000>;
|
||||
};
|
||||
|
||||
ocotp: efuse@410a6000 {
|
||||
compatible = "fsl,imx7ulp-ocotp", "syscon";
|
||||
reg = <0x410a6000 0x4000>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -35,6 +35,7 @@ config TARGET_MX7ULP_COM
|
||||
select SPL_SEPARATE_BSS if SPL
|
||||
select SPL_SERIAL if SPL
|
||||
select SUPPORT_SPL
|
||||
imply OF_UPSTREAM
|
||||
|
||||
config TARGET_MX7ULP_EVK
|
||||
bool "Support mx7ulp EVK board"
|
||||
@@ -42,6 +43,7 @@ config TARGET_MX7ULP_EVK
|
||||
select SYS_ARCH_TIMER
|
||||
select FSL_CAAM
|
||||
select ARCH_MISC_INIT
|
||||
imply OF_UPSTREAM
|
||||
|
||||
endchoice
|
||||
|
||||
|
||||
@@ -7,7 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7ulp-com"
|
||||
CONFIG_LDO_ENABLED_MODE=y
|
||||
CONFIG_TARGET_MX7ULP_COM=y
|
||||
CONFIG_SYS_BOOTM_LEN=0x1000000
|
||||
|
||||
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7ulp-evk"
|
||||
CONFIG_TARGET_MX7ULP_EVK=y
|
||||
CONFIG_SYS_BOOTM_LEN=0x1000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x60800000
|
||||
|
||||
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx7ulp-evk"
|
||||
CONFIG_TARGET_MX7ULP_EVK=y
|
||||
CONFIG_SYS_BOOTM_LEN=0x1000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x60800000
|
||||
|
||||
Reference in New Issue
Block a user