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board: phycore_imx8mm: add 1 and 4GB RAM timings

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The Phytec Tauri L is sold with multiple memory configurations beyond the
base 2 GB variant. To support these alternative capacities seamlessly,
read the physical memory size directly from the EEPROM of the underlying
phyCORE module and apply the appropriate DDR timing parameters at runtime.

Alternatively, a fixed memory configuration can still be enforced via a
dedicated Kconfig option if dynamic detection is not desired.

Note that while U-Boot correctly discovers the full physical memory bank,
the device tree excludes the memory beyond 3 GB  (below the 4 GB boundary).
This ensures that U-Boot allocations and early EFI staging buffers remain
safe from 32-bit interconnect DMA limitations inherent to some i.MX8MM
IP blocks.

Signed-off-by: INgo Rah <ingo.rah@linutronix.de>
Reviewed-by: Gregor Herburger <gregor.herburger@linutronix.de>
Reviewed-by: Benedikt Spranger <b.spranger@linutronix.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Tested-by: Yannic Moog <y.moog@phytec.de>
This commit is contained in:
INgo Rah
2026-08-03 09:31:05 -03:00
committed by Fabio Estevam
parent f2f1a1e7d2
commit 14ca9eb18d
6 changed files with 165 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
+23
View File
@@ -6,6 +6,21 @@
#include "imx8mm-u-boot.dtsi"
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* Limit memory usage below the 4 GB (32-bit) boundary.
* The i.MX8MM DMA and peripherals cannot access >32-bit
* addresses. This prevents allocation failures in UEFI mode.
*/
u_boot_sdma_shield: sdma-shield@100000000 {
reg = <0x1 0x00000000 0x0 0x40000000>;
};
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -29,6 +44,10 @@
};
};
&pinctrl_i2c1 {
bootph-pre-ram;
};
&pinctrl_uart3 {
bootph-pre-ram;
};
@@ -73,6 +92,10 @@
bootph-pre-ram;
};
&i2c1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
};
board/phytec/phycore_imx8mm/Kconfig
+65
View File
@@ -12,5 +12,70 @@ config SYS_CONFIG_NAME
config IMX_CONFIG
default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"
config PHYCORE_IMX8MM_RAM_SIZE_FIX
bool "Set phyCORE-i.MX8MM RAM size fix instead of detecting"
default false
help
RAM size is automatic being detected with the help of
the EEPROM introspection data. Set RAM size to a fix value
instead.
choice
prompt "phyCORE-i.MX8MM RAM size"
depends on PHYCORE_IMX8MM_RAM_SIZE_FIX
default PHYCORE_IMX8MM_RAM_SIZE_2GB
help
Select a fixed RAM size instead of EEPROM introspection
data.
config PHYCORE_IMX8MM_RAM_SIZE_1GB
bool "1GB RAM"
help
Set RAM size fix to 1GB for phyCORE-i.MX8MM
instead of runtime detection from EEPROM.
config PHYCORE_IMX8MM_RAM_SIZE_2GB
bool "2GB RAM"
help
Set RAM size fix to 2GB for phyCORE-i.MX8MM
instead of runtime detection from EEPROM.
config PHYCORE_IMX8MM_RAM_SIZE_4GB
bool "4GB RAM"
help
Set RAM size fix to 4GB for phyCORE-i.MX8MM
instead of runtime detection from EEPROM.
endchoice
config PHYCORE_IMX8MM_RAM_STATIC_SOM_REV
bool "Set static phyCORE-i.MX8MM SoM revision for RAM timing setup"
default false
help
phyCORE-i.MX8MM SoM revision 7 uses a updated set of optimized
RAM timings compared to revision 6 and older. Set the SoM
revision during compile time instead of being detected.
choice
prompt "phyCORE-i.MX8MM RAM timing SoM revision static config"
depends on PHYCORE_IMX8MM_RAM_STATIC_SOM_REV
default PHYCORE_IMX8MM_USE_SOM_REV_7
help
Use a fixed revision setting instead of runtime
auto detection.
config PHYCORE_IMX8MM_USE_SOM_REV_6
bool "RAM Timings for SoM Revisions 6 and older"
help
Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revisions 6
and older instead of autodetecting.
config PHYCORE_IMX8MM_USE_SOM_REV_7
bool "RAM Timings for SoM Revision 7"
help
Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revision 7
instead of autodetecting.
endchoice
source "board/phytec/common/Kconfig"
endif
board/phytec/phycore_imx8mm/phycore-imx8mm.c
+18
View File
@@ -9,6 +9,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
#include <miiphy.h>
#include <init.h>
static int setup_fec(void)
{
@@ -50,3 +51,20 @@ int board_late_init(void)
return 0;
}
int board_phys_sdram_size(phys_size_t *size)
{
if (!size)
return -EINVAL;
/*
* check various RAM sizes (1, 2 and 4 GB) otherwise
* return the default of 2GB
*/
*size = get_ram_size((void *)PHYS_SDRAM,
(long)PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
if (*size == 0)
*size = SZ_2G;
return 0;
}
board/phytec/phycore_imx8mm/spl.c
+55 -1
View File
@@ -16,11 +16,19 @@
#include <log.h>
#include <spl.h>
#include "lpddr4_timing.h"
#include "../common/imx8m_som_detection.h"
#define EEPROM_ADDR 0x51
#define EEPROM_ADDR_FALLBACK 0x59
enum phytec_imx8mm_ddr_eeprom_code {
INVALID = PHYTEC_EEPROM_INVAL,
PHYTEC_IMX8MM_DDR_1GB = 1,
PHYTEC_IMX8MM_DDR_2GB = 3,
PHYTEC_IMX8MM_DDR_4GB = 5,
};
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -42,17 +50,63 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
static void spl_dram_init(void)
{
int ret;
enum phytec_imx8mm_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
u8 rev = PHYTEC_EEPROM_INVAL;
ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
EEPROM_ADDR_FALLBACK);
if (ret)
if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX))
goto out;
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX)) {
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_1GB))
size = PHYTEC_IMX8MM_DDR_1GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_2GB))
size = PHYTEC_IMX8MM_DDR_2GB;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_4GB))
size = PHYTEC_IMX8MM_DDR_4GB;
} else {
size = phytec_get_imx8m_ddr_size(NULL);
}
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_STATIC_SOM_REV)) {
if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_6))
rev = 6;
else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_7))
rev = 7;
} else {
rev = phytec_get_rev(NULL);
}
if (rev >= 7 || rev == PHYTEC_EEPROM_INVAL) {
debug("%s: Using rev7 RAM timings.\n", __func__);
set_dram_timings_rev7();
} else {
debug("%s: Using rev6 RAM timings.\n", __func__);
}
switch (size) {
case PHYTEC_IMX8MM_DDR_1GB:
set_dram_timings_1gb();
break;
case PHYTEC_IMX8MM_DDR_2GB:
break;
case PHYTEC_IMX8MM_DDR_4GB:
set_dram_timings_4gb();
break;
default:
goto out;
}
ddr_init(&dram_timing);
return;
out:
puts("Could not detect correct RAM size. Fall back to default.\n");
set_dram_timings_rev7();
ddr_init(&dram_timing);
}
configs/imx8mm-phygate-tauri-l_defconfig
+1
View File
@@ -4,6 +4,7 @@ CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
include/configs/phycore_imx8mm.h
+3 -2
View File
@@ -28,6 +28,7 @@
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE SZ_1G /* 4GB DDR */
#endif /* __PHYCORE_IMX8MM_H */