ufs: core: move ufshci defines in a separate header
Splitting the header will help synchronizing the defines again with Linux. Acked-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Love Kumar <love.kumar@amd.com> Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-4-4c6d7994a45d@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Neil Armstrong
+1
-328
@@ -4,6 +4,7 @@
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#include <linux/types.h>
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#include <asm/io.h>
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#include "ufshci.h"
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#include "unipro.h"
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struct udevice;
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@@ -14,11 +15,6 @@ struct udevice;
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#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
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#define UFS_MAX_LUNS 0x7F
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enum {
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TASK_REQ_UPIU_SIZE_DWORDS = 8,
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TASK_RSP_UPIU_SIZE_DWORDS = 8,
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ALIGNED_UPIU_SIZE = 512,
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};
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/* UFS device power modes */
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enum ufs_dev_pwr_mode {
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@@ -84,44 +80,6 @@ enum {
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/* Offset of the response code in the UPIU header */
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#define UPIU_RSP_CODE_OFFSET 8
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/* To accommodate UFS2.0 required Command type */
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enum {
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UTP_CMD_TYPE_UFS_STORAGE = 0x1,
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};
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enum {
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UTP_SCSI_COMMAND = 0x00000000,
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UTP_NATIVE_UFS_COMMAND = 0x10000000,
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UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
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UTP_REQ_DESC_INT_CMD = 0x01000000,
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};
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/* UTP Transfer Request Data Direction (DD) */
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enum {
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UTP_NO_DATA_TRANSFER = 0x00000000,
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UTP_HOST_TO_DEVICE = 0x02000000,
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UTP_DEVICE_TO_HOST = 0x04000000,
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};
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/* Overall command status values */
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enum {
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OCS_SUCCESS = 0x0,
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OCS_INVALID_CMD_TABLE_ATTR = 0x1,
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OCS_INVALID_PRDT_ATTR = 0x2,
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OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
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OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
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OCS_PEER_COMM_FAILURE = 0x5,
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OCS_ABORTED = 0x6,
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OCS_FATAL_ERROR = 0x7,
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OCS_INVALID_COMMAND_STATUS = 0x0F,
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MASK_OCS = 0x0F,
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};
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/* The maximum length of the data byte count field in the PRDT is 256KB */
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#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
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/* The granularity of the data byte count field in the PRDT is 32-bit */
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#define PRDT_DATA_BYTE_COUNT_PAD 4
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#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
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#define QUERY_DESC_MAX_SIZE 255
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#define QUERY_DESC_MIN_SIZE 2
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@@ -297,79 +255,6 @@ enum desc_header_offset {
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QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
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};
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struct ufshcd_sg_entry {
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__le32 base_addr;
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__le32 upper_addr;
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__le32 reserved;
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__le32 size;
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};
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#define MAX_BUFF 128
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/**
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* struct utp_transfer_cmd_desc - UFS Command Descriptor structure
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* @command_upiu: Command UPIU Frame address
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* @response_upiu: Response UPIU Frame address
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* @prd_table: Physical Region Descriptor
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*/
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struct utp_transfer_cmd_desc {
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u8 command_upiu[ALIGNED_UPIU_SIZE];
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u8 response_upiu[ALIGNED_UPIU_SIZE];
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struct ufshcd_sg_entry prd_table[MAX_BUFF];
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};
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/**
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* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
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* @dword0: Descriptor Header DW0
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* @dword1: Descriptor Header DW1
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* @dword2: Descriptor Header DW2
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* @dword3: Descriptor Header DW3
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*/
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struct request_desc_header {
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__le32 dword_0;
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__le32 dword_1;
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__le32 dword_2;
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__le32 dword_3;
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};
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/**
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* struct utp_transfer_req_desc - UTRD structure
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* @header: UTRD header DW-0 to DW-3
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* @command_desc_base_addr_lo: UCD base address low DW-4
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* @command_desc_base_addr_hi: UCD base address high DW-5
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* @response_upiu_length: response UPIU length DW-6
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* @response_upiu_offset: response UPIU offset DW-6
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* @prd_table_length: Physical region descriptor length DW-7
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* @prd_table_offset: Physical region descriptor offset DW-7
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*/
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struct utp_transfer_req_desc {
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/* DW 0-3 */
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struct request_desc_header header;
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/* DW 4-5*/
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__le32 command_desc_base_addr_lo;
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__le32 command_desc_base_addr_hi;
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/* DW 6 */
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__le16 response_upiu_length;
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__le16 response_upiu_offset;
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/* DW 7 */
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__le16 prd_table_length;
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__le16 prd_table_offset;
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};
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/**
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* struct utp_upiu_header - UPIU header structure
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* @dword_0: UPIU header DW-0
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* @dword_1: UPIU header DW-1
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* @dword_2: UPIU header DW-2
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*/
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struct utp_upiu_header {
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__be32 dword_0;
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__be32 dword_1;
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__be32 dword_2;
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};
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/**
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* struct utp_upiu_query - upiu request buffer structure for
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* query request.
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@@ -403,27 +288,6 @@ struct utp_upiu_cmd {
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u8 cdb[UFS_CDB_SIZE];
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};
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/*
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* UTMRD structure.
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*/
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struct utp_task_req_desc {
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/* DW 0-3 */
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struct request_desc_header header;
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/* DW 4-11 - Task request UPIU structure */
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struct utp_upiu_header req_header;
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__be32 input_param1;
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__be32 input_param2;
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__be32 input_param3;
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__be32 __reserved1[2];
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/* DW 12-19 - Task Management Response UPIU structure */
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struct utp_upiu_header rsp_header;
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__be32 output_param1;
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__be32 output_param2;
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__be32 __reserved2[3];
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};
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/**
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* struct utp_upiu_req - general upiu request structure
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* @header:UPIU header structure DW-0 to DW-2
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@@ -551,63 +415,6 @@ struct uic_command {
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int result;
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};
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/* GenSelectorIndex calculation macros for M-PHY attributes */
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#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
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#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
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#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
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((sel) & 0xFFFF))
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#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
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#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
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#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
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/* Link Status*/
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enum link_status {
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UFSHCD_LINK_IS_DOWN = 1,
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UFSHCD_LINK_IS_UP = 2,
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};
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#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
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((sel) & 0xFFFF))
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#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
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#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
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#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
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/* UIC Commands */
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enum uic_cmd_dme {
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UIC_CMD_DME_GET = 0x01,
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UIC_CMD_DME_SET = 0x02,
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UIC_CMD_DME_PEER_GET = 0x03,
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UIC_CMD_DME_PEER_SET = 0x04,
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UIC_CMD_DME_POWERON = 0x10,
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UIC_CMD_DME_POWEROFF = 0x11,
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UIC_CMD_DME_ENABLE = 0x12,
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UIC_CMD_DME_RESET = 0x14,
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UIC_CMD_DME_END_PT_RST = 0x15,
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UIC_CMD_DME_LINK_STARTUP = 0x16,
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UIC_CMD_DME_HIBER_ENTER = 0x17,
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UIC_CMD_DME_HIBER_EXIT = 0x18,
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UIC_CMD_DME_TEST_MODE = 0x1A,
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};
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/* UIC Config result code / Generic error code */
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enum {
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UIC_CMD_RESULT_SUCCESS = 0x00,
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UIC_CMD_RESULT_INVALID_ATTR = 0x01,
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UIC_CMD_RESULT_FAILURE = 0x01,
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UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
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UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
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UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
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UIC_CMD_RESULT_BAD_INDEX = 0x05,
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UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
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UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
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UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
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UIC_CMD_RESULT_BUSY = 0x09,
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UIC_CMD_RESULT_DME_FAILURE = 0x0A,
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};
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#define MASK_UIC_COMMAND_RESULT 0xFF
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/* Host <-> Device UniPro Link state */
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enum uic_link_state {
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UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
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@@ -940,17 +747,6 @@ static inline int ufshcd_vops_device_reset(struct ufs_hba *hba)
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return 0;
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}
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/* Controller UFSHCI version */
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enum {
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UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
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UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
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UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
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UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
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UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
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UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
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UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
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};
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/* Interrupt disable masks */
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enum {
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/* Interrupt disable mask for UFSHCI v1.0 */
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@@ -964,123 +760,6 @@ enum {
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INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
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};
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/* UFSHCI Registers */
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enum {
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REG_CONTROLLER_CAPABILITIES = 0x00,
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REG_UFS_VERSION = 0x08,
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REG_CONTROLLER_DEV_ID = 0x10,
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REG_CONTROLLER_PROD_ID = 0x14,
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REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
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REG_INTERRUPT_STATUS = 0x20,
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REG_INTERRUPT_ENABLE = 0x24,
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REG_CONTROLLER_STATUS = 0x30,
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REG_CONTROLLER_ENABLE = 0x34,
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REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
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REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
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REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
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REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
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REG_UIC_ERROR_CODE_DME = 0x48,
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REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
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REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
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REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
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REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
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REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
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REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
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REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
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REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
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REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
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REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
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REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
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REG_UIC_COMMAND = 0x90,
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REG_UIC_COMMAND_ARG_1 = 0x94,
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REG_UIC_COMMAND_ARG_2 = 0x98,
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REG_UIC_COMMAND_ARG_3 = 0x9C,
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UFSHCI_REG_SPACE_SIZE = 0xA0,
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REG_UFS_CCAP = 0x100,
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REG_UFS_CRYPTOCAP = 0x104,
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UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
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};
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/* Controller capability masks */
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enum {
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MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
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MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
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MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
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MASK_64_ADDRESSING_SUPPORT = 0x01000000,
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MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
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MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
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};
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/* Interrupt Status 20h */
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#define UTP_TRANSFER_REQ_COMPL 0x1
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#define UIC_DME_END_PT_RESET 0x2
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#define UIC_ERROR 0x4
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#define UIC_TEST_MODE 0x8
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#define UIC_POWER_MODE 0x10
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#define UIC_HIBERNATE_EXIT 0x20
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#define UIC_HIBERNATE_ENTER 0x40
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#define UIC_LINK_LOST 0x80
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#define UIC_LINK_STARTUP 0x100
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#define UTP_TASK_REQ_COMPL 0x200
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#define UIC_COMMAND_COMPL 0x400
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#define DEVICE_FATAL_ERROR 0x800
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#define CONTROLLER_FATAL_ERROR 0x10000
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#define SYSTEM_BUS_FATAL_ERROR 0x20000
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#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
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UIC_HIBERNATE_EXIT |\
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UIC_POWER_MODE)
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#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
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#define UFSHCD_ERROR_MASK (UIC_ERROR |\
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DEVICE_FATAL_ERROR |\
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CONTROLLER_FATAL_ERROR |\
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SYSTEM_BUS_FATAL_ERROR)
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#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
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CONTROLLER_FATAL_ERROR |\
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SYSTEM_BUS_FATAL_ERROR)
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/* Host Controller Enable 0x34h */
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#define CONTROLLER_ENABLE 0x1
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#define CONTROLLER_DISABLE 0x0
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/* HCS - Host Controller Status 30h */
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#define DEVICE_PRESENT 0x1
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#define UTP_TRANSFER_REQ_LIST_READY 0x2
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#define UTP_TASK_REQ_LIST_READY 0x4
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#define UIC_COMMAND_READY 0x8
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#define HOST_ERROR_INDICATOR 0x10
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#define DEVICE_ERROR_INDICATOR 0x20
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#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
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#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
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UTP_TASK_REQ_LIST_READY |\
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UIC_COMMAND_READY)
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enum {
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PWR_OK = 0x0,
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PWR_LOCAL = 0x01,
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PWR_REMOTE = 0x02,
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PWR_BUSY = 0x03,
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PWR_ERROR_CAP = 0x04,
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PWR_FATAL_ERROR = 0x05,
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};
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/* UICCMD - UIC Command */
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#define COMMAND_OPCODE_MASK 0xFF
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#define GEN_SELECTOR_INDEX_MASK 0xFFFF
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#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
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#define RESET_LEVEL 0xFF
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#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
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#define CFG_RESULT_CODE_MASK 0xFF
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#define GENERIC_ERROR_CODE_MASK 0xFF
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#define ufshcd_writel(hba, val, reg) \
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writel((val), (hba)->mmio_base + (reg))
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#define ufshcd_readl(hba, reg) \
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@@ -1103,12 +782,6 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
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ufshcd_writel(hba, tmp, reg);
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}
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/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
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#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
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/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
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#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
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int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
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#endif
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@@ -0,0 +1,334 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __UFSHCI_H
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#define __UFSHCI_H
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enum {
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TASK_REQ_UPIU_SIZE_DWORDS = 8,
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TASK_RSP_UPIU_SIZE_DWORDS = 8,
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ALIGNED_UPIU_SIZE = 512,
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};
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/* To accommodate UFS2.0 required Command type */
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enum {
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UTP_CMD_TYPE_UFS_STORAGE = 0x1,
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};
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enum {
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UTP_SCSI_COMMAND = 0x00000000,
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UTP_NATIVE_UFS_COMMAND = 0x10000000,
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UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
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UTP_REQ_DESC_INT_CMD = 0x01000000,
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};
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/* UTP Transfer Request Data Direction (DD) */
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enum {
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UTP_NO_DATA_TRANSFER = 0x00000000,
|
||||
UTP_HOST_TO_DEVICE = 0x02000000,
|
||||
UTP_DEVICE_TO_HOST = 0x04000000,
|
||||
};
|
||||
|
||||
/* Overall command status values */
|
||||
enum {
|
||||
OCS_SUCCESS = 0x0,
|
||||
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
|
||||
OCS_INVALID_PRDT_ATTR = 0x2,
|
||||
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
|
||||
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
|
||||
OCS_PEER_COMM_FAILURE = 0x5,
|
||||
OCS_ABORTED = 0x6,
|
||||
OCS_FATAL_ERROR = 0x7,
|
||||
OCS_INVALID_COMMAND_STATUS = 0x0F,
|
||||
MASK_OCS = 0x0F,
|
||||
};
|
||||
|
||||
/* The maximum length of the data byte count field in the PRDT is 256KB */
|
||||
#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
|
||||
/* The granularity of the data byte count field in the PRDT is 32-bit */
|
||||
#define PRDT_DATA_BYTE_COUNT_PAD 4
|
||||
|
||||
/* Controller UFSHCI version */
|
||||
enum {
|
||||
UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
|
||||
UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
|
||||
UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
|
||||
UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
|
||||
UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
|
||||
UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
|
||||
UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
|
||||
};
|
||||
|
||||
/* UFSHCI Registers */
|
||||
enum {
|
||||
REG_CONTROLLER_CAPABILITIES = 0x00,
|
||||
REG_UFS_VERSION = 0x08,
|
||||
REG_CONTROLLER_DEV_ID = 0x10,
|
||||
REG_CONTROLLER_PROD_ID = 0x14,
|
||||
REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
|
||||
REG_INTERRUPT_STATUS = 0x20,
|
||||
REG_INTERRUPT_ENABLE = 0x24,
|
||||
REG_CONTROLLER_STATUS = 0x30,
|
||||
REG_CONTROLLER_ENABLE = 0x34,
|
||||
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
|
||||
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
|
||||
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
|
||||
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
|
||||
REG_UIC_ERROR_CODE_DME = 0x48,
|
||||
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
|
||||
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
|
||||
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
|
||||
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
|
||||
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
|
||||
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
|
||||
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
|
||||
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
|
||||
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
|
||||
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
|
||||
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
|
||||
REG_UIC_COMMAND = 0x90,
|
||||
REG_UIC_COMMAND_ARG_1 = 0x94,
|
||||
REG_UIC_COMMAND_ARG_2 = 0x98,
|
||||
REG_UIC_COMMAND_ARG_3 = 0x9C,
|
||||
|
||||
UFSHCI_REG_SPACE_SIZE = 0xA0,
|
||||
|
||||
REG_UFS_CCAP = 0x100,
|
||||
REG_UFS_CRYPTOCAP = 0x104,
|
||||
|
||||
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
|
||||
};
|
||||
|
||||
/* Controller capability masks */
|
||||
enum {
|
||||
MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
|
||||
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
|
||||
MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
|
||||
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
|
||||
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
|
||||
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
|
||||
};
|
||||
|
||||
/* Interrupt Status 20h */
|
||||
#define UTP_TRANSFER_REQ_COMPL 0x1
|
||||
#define UIC_DME_END_PT_RESET 0x2
|
||||
#define UIC_ERROR 0x4
|
||||
#define UIC_TEST_MODE 0x8
|
||||
#define UIC_POWER_MODE 0x10
|
||||
#define UIC_HIBERNATE_EXIT 0x20
|
||||
#define UIC_HIBERNATE_ENTER 0x40
|
||||
#define UIC_LINK_LOST 0x80
|
||||
#define UIC_LINK_STARTUP 0x100
|
||||
#define UTP_TASK_REQ_COMPL 0x200
|
||||
#define UIC_COMMAND_COMPL 0x400
|
||||
#define DEVICE_FATAL_ERROR 0x800
|
||||
#define CONTROLLER_FATAL_ERROR 0x10000
|
||||
#define SYSTEM_BUS_FATAL_ERROR 0x20000
|
||||
|
||||
#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
|
||||
UIC_HIBERNATE_EXIT |\
|
||||
UIC_POWER_MODE)
|
||||
|
||||
#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
|
||||
|
||||
#define UFSHCD_ERROR_MASK (UIC_ERROR |\
|
||||
DEVICE_FATAL_ERROR |\
|
||||
CONTROLLER_FATAL_ERROR |\
|
||||
SYSTEM_BUS_FATAL_ERROR)
|
||||
|
||||
#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
|
||||
CONTROLLER_FATAL_ERROR |\
|
||||
SYSTEM_BUS_FATAL_ERROR)
|
||||
|
||||
/* Host Controller Enable 0x34h */
|
||||
#define CONTROLLER_ENABLE 0x1
|
||||
#define CONTROLLER_DISABLE 0x0
|
||||
/* HCS - Host Controller Status 30h */
|
||||
#define DEVICE_PRESENT 0x1
|
||||
#define UTP_TRANSFER_REQ_LIST_READY 0x2
|
||||
#define UTP_TASK_REQ_LIST_READY 0x4
|
||||
#define UIC_COMMAND_READY 0x8
|
||||
#define HOST_ERROR_INDICATOR 0x10
|
||||
#define DEVICE_ERROR_INDICATOR 0x20
|
||||
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
|
||||
|
||||
#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
|
||||
UTP_TASK_REQ_LIST_READY |\
|
||||
UIC_COMMAND_READY)
|
||||
|
||||
enum {
|
||||
PWR_OK = 0x0,
|
||||
PWR_LOCAL = 0x01,
|
||||
PWR_REMOTE = 0x02,
|
||||
PWR_BUSY = 0x03,
|
||||
PWR_ERROR_CAP = 0x04,
|
||||
PWR_FATAL_ERROR = 0x05,
|
||||
};
|
||||
|
||||
/* UICCMD - UIC Command */
|
||||
#define COMMAND_OPCODE_MASK 0xFF
|
||||
#define GEN_SELECTOR_INDEX_MASK 0xFFFF
|
||||
|
||||
#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
|
||||
#define RESET_LEVEL 0xFF
|
||||
|
||||
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
|
||||
#define CFG_RESULT_CODE_MASK 0xFF
|
||||
#define GENERIC_ERROR_CODE_MASK 0xFF
|
||||
|
||||
/* GenSelectorIndex calculation macros for M-PHY attributes */
|
||||
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
|
||||
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
|
||||
|
||||
#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
|
||||
((sel) & 0xFFFF))
|
||||
#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
|
||||
#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
|
||||
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
|
||||
|
||||
/* Link Status*/
|
||||
enum link_status {
|
||||
UFSHCD_LINK_IS_DOWN = 1,
|
||||
UFSHCD_LINK_IS_UP = 2,
|
||||
};
|
||||
|
||||
#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
|
||||
((sel) & 0xFFFF))
|
||||
#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
|
||||
#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
|
||||
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
|
||||
|
||||
/* UIC Commands */
|
||||
enum uic_cmd_dme {
|
||||
UIC_CMD_DME_GET = 0x01,
|
||||
UIC_CMD_DME_SET = 0x02,
|
||||
UIC_CMD_DME_PEER_GET = 0x03,
|
||||
UIC_CMD_DME_PEER_SET = 0x04,
|
||||
UIC_CMD_DME_POWERON = 0x10,
|
||||
UIC_CMD_DME_POWEROFF = 0x11,
|
||||
UIC_CMD_DME_ENABLE = 0x12,
|
||||
UIC_CMD_DME_RESET = 0x14,
|
||||
UIC_CMD_DME_END_PT_RST = 0x15,
|
||||
UIC_CMD_DME_LINK_STARTUP = 0x16,
|
||||
UIC_CMD_DME_HIBER_ENTER = 0x17,
|
||||
UIC_CMD_DME_HIBER_EXIT = 0x18,
|
||||
UIC_CMD_DME_TEST_MODE = 0x1A,
|
||||
};
|
||||
|
||||
/* UIC Config result code / Generic error code */
|
||||
enum {
|
||||
UIC_CMD_RESULT_SUCCESS = 0x00,
|
||||
UIC_CMD_RESULT_INVALID_ATTR = 0x01,
|
||||
UIC_CMD_RESULT_FAILURE = 0x01,
|
||||
UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
|
||||
UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
|
||||
UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
|
||||
UIC_CMD_RESULT_BAD_INDEX = 0x05,
|
||||
UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
|
||||
UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
|
||||
UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
|
||||
UIC_CMD_RESULT_BUSY = 0x09,
|
||||
UIC_CMD_RESULT_DME_FAILURE = 0x0A,
|
||||
};
|
||||
|
||||
#define MASK_UIC_COMMAND_RESULT 0xFF
|
||||
|
||||
/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
|
||||
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
|
||||
|
||||
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
|
||||
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
|
||||
|
||||
struct ufshcd_sg_entry {
|
||||
__le32 base_addr;
|
||||
__le32 upper_addr;
|
||||
__le32 reserved;
|
||||
__le32 size;
|
||||
};
|
||||
|
||||
#define MAX_BUFF 128
|
||||
/**
|
||||
* struct utp_transfer_cmd_desc - UFS Command Descriptor structure
|
||||
* @command_upiu: Command UPIU Frame address
|
||||
* @response_upiu: Response UPIU Frame address
|
||||
* @prd_table: Physical Region Descriptor
|
||||
*/
|
||||
struct utp_transfer_cmd_desc {
|
||||
u8 command_upiu[ALIGNED_UPIU_SIZE];
|
||||
u8 response_upiu[ALIGNED_UPIU_SIZE];
|
||||
struct ufshcd_sg_entry prd_table[MAX_BUFF];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
|
||||
* @dword0: Descriptor Header DW0
|
||||
* @dword1: Descriptor Header DW1
|
||||
* @dword2: Descriptor Header DW2
|
||||
* @dword3: Descriptor Header DW3
|
||||
*/
|
||||
struct request_desc_header {
|
||||
__le32 dword_0;
|
||||
__le32 dword_1;
|
||||
__le32 dword_2;
|
||||
__le32 dword_3;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct utp_transfer_req_desc - UTRD structure
|
||||
* @header: UTRD header DW-0 to DW-3
|
||||
* @command_desc_base_addr_lo: UCD base address low DW-4
|
||||
* @command_desc_base_addr_hi: UCD base address high DW-5
|
||||
* @response_upiu_length: response UPIU length DW-6
|
||||
* @response_upiu_offset: response UPIU offset DW-6
|
||||
* @prd_table_length: Physical region descriptor length DW-7
|
||||
* @prd_table_offset: Physical region descriptor offset DW-7
|
||||
*/
|
||||
struct utp_transfer_req_desc {
|
||||
/* DW 0-3 */
|
||||
struct request_desc_header header;
|
||||
|
||||
/* DW 4-5*/
|
||||
__le32 command_desc_base_addr_lo;
|
||||
__le32 command_desc_base_addr_hi;
|
||||
|
||||
/* DW 6 */
|
||||
__le16 response_upiu_length;
|
||||
__le16 response_upiu_offset;
|
||||
|
||||
/* DW 7 */
|
||||
__le16 prd_table_length;
|
||||
__le16 prd_table_offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct utp_upiu_header - UPIU header structure
|
||||
* @dword_0: UPIU header DW-0
|
||||
* @dword_1: UPIU header DW-1
|
||||
* @dword_2: UPIU header DW-2
|
||||
*/
|
||||
struct utp_upiu_header {
|
||||
__be32 dword_0;
|
||||
__be32 dword_1;
|
||||
__be32 dword_2;
|
||||
};
|
||||
|
||||
/*
|
||||
* UTMRD structure.
|
||||
*/
|
||||
struct utp_task_req_desc {
|
||||
/* DW 0-3 */
|
||||
struct request_desc_header header;
|
||||
|
||||
/* DW 4-11 - Task request UPIU structure */
|
||||
struct utp_upiu_header req_header;
|
||||
__be32 input_param1;
|
||||
__be32 input_param2;
|
||||
__be32 input_param3;
|
||||
__be32 __reserved1[2];
|
||||
|
||||
/* DW 12-19 - Task Management Response UPIU structure */
|
||||
struct utp_upiu_header rsp_header;
|
||||
__be32 output_param1;
|
||||
__be32 output_param2;
|
||||
__be32 __reserved2[3];
|
||||
};
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user