net: dwc_eth_xgmac_socfpga: Add support for distinct mac-mode and phy mode.

This patch adds support for configuring the ethernet MAC mode independently
from the PHY mode on our SoC FPGA board. Specifically, this is necessary
for a scenario where the ethernet controller MAC is connected to the
FPGA HVIO with a different GMII interface, and the FPGA output is routed
to the PHY using a RGMII interface.

To support this configuration, a mechanism is introduced to handle
separate MAC mode settings, ensuring that the MAC controller and PHY
can operate correctly with their respective interface modes.

If mac-mode is not defined, the MAC mode will default to the PHY mode,
ensuring compatibility and proper operation between the MAC and PHY.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Boon Khai Ng
2025-01-24 09:56:22 +08:00
committed by Tien Fong Chee
parent d22da11742
commit 1130ad4ee4
+25 -1
View File
@@ -29,6 +29,25 @@
#define SOCFPGA_XGMAC_SYSCON_ARG_COUNT 2
phy_interface_t dwxgmac_of_get_mac_mode(struct udevice *dev)
{
const char *mac_mode;
int i;
debug("%s(dev=%p):\n", __func__, dev);
mac_mode = dev_read_string(dev, "mac-mode");
if (!mac_mode)
return PHY_INTERFACE_MODE_NA;
if (mac_mode) {
for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) {
if (!strcmp(mac_mode, phy_interface_strings[i]))
return i;
}
}
return PHY_INTERFACE_MODE_NA;
}
static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
{
struct xgmac_priv *xgmac = dev_get_priv(dev);
@@ -66,12 +85,17 @@ static int xgmac_probe_resources_socfpga(struct udevice *dev)
struct ofnode_phandle_args args;
void *range;
phy_interface_t interface;
phy_interface_t mac_mode;
int ret;
u32 modereg;
interface = xgmac->config->interface(dev);
mac_mode = dwxgmac_of_get_mac_mode(dev);
switch (interface) {
if (mac_mode == PHY_INTERFACE_MODE_NA)
mac_mode = interface;
switch (mac_mode) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;