arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading
Add CMA (Contiguous Memory Allocator) reserved-memory regions to all Xilinx arm64 board device trees to support runtime FPGA programming. The CMA pool uses dynamic allocation constrained to the low 2 GB DDR region via alloc-ranges so that the kernel places it within the 32-bit addressable space. CMA sizes are chosen per silicon family to accommodate the maximum PL bitstream/PDI size: - Kria K24 SOM: 64 MB - ZynqMP boards: 128 MB For Kria K24 SOM the CMA inherited from K26 is overridden to 64 MB. For Kria SOMs, the CMA node is added to the SOM DTS only, not to carrier board overlays. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/837e21582e886f1be9f95901109745ac5a8b2a25.1780991287.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP SM-K24 RevA
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*
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* (C) Copyright 2020 - 2021, Xilinx, Inc.
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* (C) Copyright 2022, Advanced Micro Devices, Inc.
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* (C) Copyright 2022-2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -21,3 +21,8 @@
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reg = <0 0 0 0x80000000>;
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};
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};
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&cma {
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size = <0x0 0x4000000>;
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alignment = <0x0 0x4000000>;
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};
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
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*
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* (C) Copyright 2020 - 2021, Xilinx, Inc.
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* (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
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* (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -61,6 +61,15 @@
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reg = <0x0 0x7ff00000 0x0 0x100000>;
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no-map;
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};
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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gpio-keys {
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@@ -31,6 +31,21 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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};
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&dcc {
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@@ -32,6 +32,21 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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};
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&dcc {
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP zc1751-xm015-dc1
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*
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* (C) Copyright 2015 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -41,6 +41,21 @@
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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clock_si5338_0: clk27 { /* u55 SI5338-GM */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP zc1751-xm016-dc2
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*
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* (C) Copyright 2015 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -39,6 +39,21 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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};
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&can0 {
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@@ -39,6 +39,21 @@
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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clock_si5338_2: clk26 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -38,6 +38,21 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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};
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&can0 {
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@@ -37,6 +37,21 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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};
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&fpd_dma_chan1 {
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP ZCU100 revC
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*
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* (C) Copyright 2016 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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* Nathalie Chan King Choy
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@@ -47,6 +47,21 @@
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP ZCU102 RevA
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*
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* (C) Copyright 2015 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -45,6 +45,21 @@
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP ZCU104
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*
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* (C) Copyright 2017 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -43,6 +43,21 @@
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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clock_8t49n287_5: clk125 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP ZCU104
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*
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* (C) Copyright 2017 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -43,6 +43,21 @@
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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ina226 {
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compatible = "iio-hwmon";
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io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP ZCU106
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*
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* (C) Copyright 2016 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -45,6 +45,21 @@
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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@@ -3,7 +3,7 @@
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* dts file for Xilinx ZynqMP ZCU111
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*
|
||||
* (C) Copyright 2017 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*
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* Michal Simek <michal.simek@amd.com>
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*/
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@@ -45,6 +45,21 @@
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/* Another 4GB connected to PL */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
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linux,cma-default;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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@@ -32,6 +32,21 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
|
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
|
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reusable;
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size = <0x0 0x8000000>;
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alignment = <0x0 0x8000000>;
|
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
|
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linux,cma-default;
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};
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};
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};
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&dcc {
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@@ -35,6 +35,21 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
|
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#size-cells = <2>;
|
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ranges;
|
||||
|
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cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
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reusable;
|
||||
size = <0x0 0x8000000>;
|
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alignment = <0x0 0x8000000>;
|
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alloc-ranges = <0x0 0x0 0x0 0x80000000>;
|
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linux,cma-default;
|
||||
};
|
||||
};
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||||
};
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||||
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&dcc {
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||||
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@@ -36,6 +36,21 @@
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device_type = "memory";
|
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reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x8000000>;
|
||||
alignment = <0x0 0x8000000>;
|
||||
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
||||
@@ -43,6 +43,21 @@
|
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x8000000>;
|
||||
alignment = <0x0 0x8000000>;
|
||||
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
@@ -43,6 +43,21 @@
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x8000000>;
|
||||
alignment = <0x0 0x8000000>;
|
||||
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* dts file for Xilinx ZynqMP ZCU670 (67DR)
|
||||
*
|
||||
* (C) Copyright 2017 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
@@ -46,6 +46,21 @@
|
||||
/* Another 4GB connected to PL */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x8000000>;
|
||||
alignment = <0x0 0x8000000>;
|
||||
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* dts file for Xilinx ZynqMP ZCU670 (67DR) revB
|
||||
*
|
||||
* (C) Copyright 2017 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
* (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
@@ -46,6 +46,21 @@
|
||||
/* Another 4GB connected to PL */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cma: linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x8000000>;
|
||||
alignment = <0x0 0x8000000>;
|
||||
alloc-ranges = <0x0 0x0 0x0 0x80000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
Reference in New Issue
Block a user