imx93_var_som: Switch to OF_UPSTREAM
Enable OF_UPSTREAM and remove local device tree files in favor of upstream device trees from Linux kernel. Signed-off-by: Alice Guo <alice.guo@nxp.com>
This commit is contained in:
Alice Guo
Fabio Estevam
@@ -878,9 +878,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
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imx8mp-dhcom-picoitx.dtb
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dtb-$(CONFIG_ARCH_IMX9) += \
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imx93-var-som-symphony.dtb
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dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
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imxrt1170-evk.dtb \
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@@ -1,323 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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* Copyright 2023 Variscite Ltd.
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*/
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/dts-v1/;
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#include "imx93-var-som.dtsi"
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/{
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model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
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compatible = "variscite,var-som-mx93-symphony",
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"variscite,var-som-mx93", "fsl,imx93";
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aliases {
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ethernet0 = &eqos;
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ethernet1 = &fec;
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};
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chosen {
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stdout-path = &lpuart1;
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};
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/*
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* Needed only for Symphony <= v1.5
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*/
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reg_fec_phy: regulator-fec-phy {
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compatible = "regulator-fixed";
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regulator-name = "fec-phy";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <20000>;
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gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
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off-on-delay-us = <20000>;
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enable-active-high;
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};
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reg_vref_1v8: regulator-adc-vref {
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compatible = "regulator-fixed";
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regulator-name = "vref_1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ethosu_mem: ethosu-region@88000000 {
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compatible = "shared-dma-pool";
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reusable;
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reg = <0x0 0x88000000 0x0 0x8000000>;
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};
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vdev0vring0: vdev0vring0@87ee0000 {
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reg = <0 0x87ee0000 0 0x8000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@87ee8000 {
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reg = <0 0x87ee8000 0 0x8000>;
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no-map;
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};
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vdev1vring0: vdev1vring0@87ef0000 {
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reg = <0 0x87ef0000 0 0x8000>;
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no-map;
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};
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vdev1vring1: vdev1vring1@87ef8000 {
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reg = <0 0x87ef8000 0 0x8000>;
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no-map;
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};
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rsc_table: rsc-table@2021f000 {
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reg = <0 0x2021f000 0 0x1000>;
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no-map;
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};
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vdevbuffer: vdevbuffer@87f00000 {
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compatible = "shared-dma-pool";
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reg = <0 0x87f00000 0 0x100000>;
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no-map;
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};
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ele_reserved: ele-reserved@87de0000 {
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compatible = "shared-dma-pool";
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reg = <0 0x87de0000 0 0x100000>;
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no-map;
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};
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};
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};
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/* Use external instead of internal RTC*/
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&bbnsm_rtc {
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status = "disabled";
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};
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&eqos {
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mdio {
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ethphy1: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <5>;
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qca,disable-smarteee;
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eee-broken-1000t;
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reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <20000>;
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vddio-supply = <&vddio1>;
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vddio1: vddio-regulator {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii";
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phy-handle = <ðphy1>;
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phy-supply = <®_fec_phy>;
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status = "okay";
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
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MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
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MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
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MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
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MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
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MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
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MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
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MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
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MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
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MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
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MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX93_PAD_PDM_CLK__CAN1_TX 0x139e
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MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
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MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
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>;
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};
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pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
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fsl,pins = <
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MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
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MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
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>;
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};
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pinctrl_lpi2c5: lpi2c5grp {
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fsl,pins = <
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MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
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MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
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>;
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};
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pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
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fsl,pins = <
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MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
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MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
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>;
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};
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pinctrl_pca9534: pca9534grp {
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fsl,pins = <
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MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
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MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
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>;
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};
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};
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&lpi2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
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pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
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scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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/* DS1337 RTC module */
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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};
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&lpi2c5 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c5>;
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pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
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pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
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scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pca9534: gpio@20 {
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compatible = "nxp,pca9534";
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reg = <0x20>;
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gpio-controller;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pca9534>;
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interrupt-parent = <&gpio3>;
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interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
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#gpio-cells = <2>;
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wakeup-source;
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};
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};
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/* Console */
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
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clock-names = "ipg", "per";
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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disable-over-current;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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hnp-disable;
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srp-disable;
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adp-disable;
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disable-over-current;
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status = "okay";
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};
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/* SD */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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no-sdio;
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no-mmc;
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};
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/* Watchdog */
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&wdog3 {
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status = "okay";
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};
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@@ -1,111 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 NXP
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* Copyright 2023 Variscite Ltd.
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*/
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/dts-v1/;
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#include "imx93.dtsi"
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/{
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model = "Variscite VAR-SOM-MX93 module";
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compatible = "variscite,var-som-mx93", "fsl,imx93";
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mmc_pwrseq: mmc-pwrseq {
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compatible = "mmc-pwrseq-simple";
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post-power-on-delay-ms = <100>;
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power-off-delay-us = <10000>;
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reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
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<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
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};
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reg_eqos_phy: regulator-eqos-phy {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_eqos_phy>;
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regulator-name = "eth_phy_pwr";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100000>;
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regulator-always-on;
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};
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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phy-supply = <®_eqos_phy>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <1000000>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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eee-broken-1000t;
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};
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};
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
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MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
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MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
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MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
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MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
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MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
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MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
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MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
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MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
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MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
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MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
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MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
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MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
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>;
|
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};
|
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pinctrl_reg_eqos_phy: regeqosgrp {
|
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fsl,pins = <
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MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
|
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
|
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
|
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
|
||||
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
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||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,906 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx93-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/fsl,imx93-power.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
#include "imx93-pinfunc.h"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
i2c0 = &lpi2c1;
|
||||
i2c1 = &lpi2c2;
|
||||
i2c2 = &lpi2c3;
|
||||
i2c3 = &lpi2c4;
|
||||
i2c4 = &lpi2c5;
|
||||
i2c5 = &lpi2c6;
|
||||
i2c6 = &lpi2c7;
|
||||
i2c7 = &lpi2c8;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &lpuart1;
|
||||
serial1 = &lpuart2;
|
||||
serial2 = &lpuart3;
|
||||
serial3 = &lpuart4;
|
||||
serial4 = &lpuart5;
|
||||
serial5 = &lpuart6;
|
||||
serial6 = &lpuart7;
|
||||
serial7 = &lpuart8;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A55_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
A55_1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
osc_24m: clock-osc-24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc_24m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <24000000>;
|
||||
arm,no-tick-in-suspend;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0 0x48000000 0 0x10000>,
|
||||
<0 0x48040000 0 0xc0000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
||||
trips {
|
||||
cpu_alert: cpu-alert {
|
||||
temperature = <80000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit: cpu-crit {
|
||||
temperature = <90000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop2: usbphynop2 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0x80000000>,
|
||||
<0x28000000 0x0 0x28000000 0x10000000>;
|
||||
|
||||
aips1: bus@44000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x44000000 0x800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
anomix_ns_gpr: syscon@44210000 {
|
||||
compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
|
||||
reg = <0x44210000 0x1000>;
|
||||
};
|
||||
|
||||
mu1: mailbox@44230000 {
|
||||
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
|
||||
reg = <0x44230000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_MU1_B_GATE>;
|
||||
#mbox-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system_counter: timer@44290000 {
|
||||
compatible = "nxp,sysctr-timer";
|
||||
reg = <0x44290000 0x30000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc_24m>;
|
||||
clock-names = "per";
|
||||
nxp,no-divider;
|
||||
};
|
||||
|
||||
tpm1: pwm@44310000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x44310000 0x1000>;
|
||||
clocks = <&clk IMX93_CLK_TPM1_GATE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tpm2: pwm@44320000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x44320000 0x10000>;
|
||||
clocks = <&clk IMX93_CLK_TPM2_GATE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c1: i2c@44340000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x44340000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
|
||||
<&clk IMX93_CLK_BUS_AON>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c2: i2c@44350000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x44350000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
|
||||
<&clk IMX93_CLK_BUS_AON>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi1: spi@44360000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x44360000 0x10000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
|
||||
<&clk IMX93_CLK_BUS_AON>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi2: spi@44370000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x44370000 0x10000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
|
||||
<&clk IMX93_CLK_BUS_AON>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@44380000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x44380000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@44390000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x44390000 0x1000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART2_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flexcan1: can@443a0000 {
|
||||
compatible = "fsl,imx93-flexcan";
|
||||
reg = <0x443a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_BUS_AON>,
|
||||
<&clk IMX93_CLK_CAN1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
assigned-clocks = <&clk IMX93_CLK_CAN1>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
fsl,clk-source = /bits/ 8 <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: pinctrl@443c0000 {
|
||||
compatible = "fsl,imx93-iomuxc";
|
||||
reg = <0x443c0000 0x10000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
bbnsm: bbnsm@44440000 {
|
||||
compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
|
||||
reg = <0x44440000 0x10000>;
|
||||
|
||||
bbnsm_rtc: rtc {
|
||||
compatible = "nxp,imx93-bbnsm-rtc";
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bbnsm_pwrkey: pwrkey {
|
||||
compatible = "nxp,imx93-bbnsm-pwrkey";
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
};
|
||||
|
||||
clk: clock-controller@44450000 {
|
||||
compatible = "fsl,imx93-ccm";
|
||||
reg = <0x44450000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
src: system-controller@44460000 {
|
||||
compatible = "fsl,imx93-src", "syscon";
|
||||
reg = <0x44460000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mediamix: power-domain@44462400 {
|
||||
compatible = "fsl,imx93-src-slice";
|
||||
reg = <0x44462400 0x400>, <0x44465800 0x400>;
|
||||
#power-domain-cells = <0>;
|
||||
clocks = <&clk IMX93_CLK_MEDIA_AXI>,
|
||||
<&clk IMX93_CLK_MEDIA_APB>;
|
||||
};
|
||||
|
||||
mlmix: power-domain@44461800 {
|
||||
compatible = "fsl,imx93-src-slice";
|
||||
reg = <0x44461800 0x400>, <0x44464800 0x400>;
|
||||
#power-domain-cells = <0>;
|
||||
clocks = <&clk IMX93_CLK_ML_APB>,
|
||||
<&clk IMX93_CLK_ML>;
|
||||
};
|
||||
};
|
||||
|
||||
anatop: anatop@44480000 {
|
||||
compatible = "fsl,imx93-anatop", "syscon";
|
||||
reg = <0x44480000 0x10000>;
|
||||
};
|
||||
|
||||
tmu: tmu@44482000 {
|
||||
compatible = "fsl,imx93-tmu";
|
||||
reg = <0x44482000 0x1000>;
|
||||
clocks = <&clk IMX93_CLK_TMC_GATE>;
|
||||
little-endian;
|
||||
fsl,tmu-calibration = <0x0000000e 0x800000da
|
||||
0x00000029 0x800000e9
|
||||
0x00000056 0x80000102
|
||||
0x000000a2 0x8000012a
|
||||
0x00000116 0x80000166
|
||||
0x00000195 0x800001a7
|
||||
0x000001b2 0x800001b6>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
adc1: adc@44530000 {
|
||||
compatible = "nxp,imx93-adc";
|
||||
reg = <0x44530000 0x10000>;
|
||||
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_ADC1_GATE>;
|
||||
clock-names = "ipg";
|
||||
#io-channel-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips2: bus@42000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x42000000 0x800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
wakeupmix_gpr: syscon@42420000 {
|
||||
compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
|
||||
reg = <0x42420000 0x1000>;
|
||||
};
|
||||
|
||||
mu2: mailbox@42440000 {
|
||||
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
|
||||
reg = <0x42440000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_MU2_B_GATE>;
|
||||
#mbox-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: wdog@42490000 {
|
||||
compatible = "fsl,imx93-wdt";
|
||||
reg = <0x42490000 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_WDOG3_GATE>;
|
||||
timeout-sec = <40>;
|
||||
};
|
||||
|
||||
tpm3: pwm@424e0000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x424e0000 0x1000>;
|
||||
clocks = <&clk IMX93_CLK_TPM3_GATE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tpm4: pwm@424f0000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x424f0000 0x10000>;
|
||||
clocks = <&clk IMX93_CLK_TPM4_GATE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tpm5: pwm@42500000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x42500000 0x10000>;
|
||||
clocks = <&clk IMX93_CLK_TPM5_GATE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tpm6: pwm@42510000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x42510000 0x10000>;
|
||||
clocks = <&clk IMX93_CLK_TPM6_GATE>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c3: i2c@42530000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x42530000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c4: i2c@42540000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x42540000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi3: spi@42550000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x42550000 0x10000>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi4: spi@42560000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x42560000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@42570000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x42570000 0x1000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART3_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@42580000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x42580000 0x1000>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART4_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@42590000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x42590000 0x1000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART5_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart6: serial@425a0000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x425a0000 0x1000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART6_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flexcan2: can@425b0000 {
|
||||
compatible = "fsl,imx93-flexcan";
|
||||
reg = <0x425b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
||||
<&clk IMX93_CLK_CAN2_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
assigned-clocks = <&clk IMX93_CLK_CAN2>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
fsl,clk-source = /bits/ 8 <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
flexspi1: spi@425e0000 {
|
||||
compatible = "nxp,imx8mm-fspi";
|
||||
reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
|
||||
reg-names = "fspi_base", "fspi_mmap";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
|
||||
<&clk IMX93_CLK_FLEXSPI1_GATE>;
|
||||
clock-names = "fspi_en", "fspi";
|
||||
assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart7: serial@42690000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x42690000 0x1000>;
|
||||
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART7_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart8: serial@426a0000 {
|
||||
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x426a0000 0x1000>;
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c5: i2c@426b0000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x426b0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c6: i2c@426c0000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x426c0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c7: i2c@426d0000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x426d0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c8: i2c@426e0000 {
|
||||
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x426e0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi5: spi@426f0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x426f0000 0x10000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi6: spi@42700000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x42700000 0x10000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi7: spi@42710000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x42710000 0x10000>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi8: spi@42720000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
||||
reg = <0x42720000 0x10000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
|
||||
<&clk IMX93_CLK_BUS_WAKEUP>;
|
||||
clock-names = "per", "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
aips3: bus@42800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x42800000 0x800000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usdhc1: mmc@42850000 {
|
||||
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x42850000 0x10000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
||||
<&clk IMX93_CLK_WAKEUP_AXI>,
|
||||
<&clk IMX93_CLK_USDHC1_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <8>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@42860000 {
|
||||
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x42860000 0x10000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
||||
<&clk IMX93_CLK_WAKEUP_AXI>,
|
||||
<&clk IMX93_CLK_USDHC2_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eqos: ethernet@428a0000 {
|
||||
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
|
||||
reg = <0x428a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
|
||||
<&clk IMX93_CLK_ENET_QOS_GATE>,
|
||||
<&clk IMX93_CLK_ENET_TIMER2>,
|
||||
<&clk IMX93_CLK_ENET>,
|
||||
<&clk IMX93_CLK_ENET_QOS_GATE>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
|
||||
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
|
||||
<&clk IMX93_CLK_ENET>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
|
||||
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
|
||||
assigned-clock-rates = <100000000>, <250000000>;
|
||||
intf_mode = <&wakeupmix_gpr 0x28>;
|
||||
snps,clk-csr = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec: ethernet@42890000 {
|
||||
compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x42890000 0x10000>;
|
||||
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_ENET1_GATE>,
|
||||
<&clk IMX93_CLK_ENET1_GATE>,
|
||||
<&clk IMX93_CLK_ENET_TIMER1>,
|
||||
<&clk IMX93_CLK_ENET_REF>,
|
||||
<&clk IMX93_CLK_ENET_REF_PHY>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
|
||||
<&clk IMX93_CLK_ENET_REF>,
|
||||
<&clk IMX93_CLK_ENET_REF_PHY>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
|
||||
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
|
||||
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
||||
assigned-clock-rates = <100000000>, <250000000>, <50000000>;
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: mmc@428b0000 {
|
||||
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
||||
reg = <0x428b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
||||
<&clk IMX93_CLK_WAKEUP_AXI>,
|
||||
<&clk IMX93_CLK_USDHC3_GATE>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@43810080 {
|
||||
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x43810080 0x1000>, <0x43810040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&clk IMX93_CLK_GPIO2_GATE>,
|
||||
<&clk IMX93_CLK_GPIO2_GATE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc 0 4 30>;
|
||||
};
|
||||
|
||||
gpio3: gpio@43820080 {
|
||||
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x43820080 0x1000>, <0x43820040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&clk IMX93_CLK_GPIO3_GATE>,
|
||||
<&clk IMX93_CLK_GPIO3_GATE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
|
||||
<&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
|
||||
};
|
||||
|
||||
gpio4: gpio@43830080 {
|
||||
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x43830080 0x1000>, <0x43830040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&clk IMX93_CLK_GPIO4_GATE>,
|
||||
<&clk IMX93_CLK_GPIO4_GATE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@47400080 {
|
||||
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
||||
reg = <0x47400080 0x1000>, <0x47400040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&clk IMX93_CLK_GPIO1_GATE>,
|
||||
<&clk IMX93_CLK_GPIO1_GATE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc 0 92 16>;
|
||||
};
|
||||
|
||||
s4muap: mailbox@47520000 {
|
||||
compatible = "fsl,imx93-mu-s4";
|
||||
reg = <0x47520000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
media_blk_ctrl: system-controller@4ac10000 {
|
||||
compatible = "fsl,imx93-media-blk-ctrl", "syscon";
|
||||
reg = <0x4ac10000 0x10000>;
|
||||
power-domains = <&mediamix>;
|
||||
clocks = <&clk IMX93_CLK_MEDIA_APB>,
|
||||
<&clk IMX93_CLK_MEDIA_AXI>,
|
||||
<&clk IMX93_CLK_NIC_MEDIA_GATE>,
|
||||
<&clk IMX93_CLK_MEDIA_DISP_PIX>,
|
||||
<&clk IMX93_CLK_CAM_PIX>,
|
||||
<&clk IMX93_CLK_PXP_GATE>,
|
||||
<&clk IMX93_CLK_LCDIF_GATE>,
|
||||
<&clk IMX93_CLK_ISI_GATE>,
|
||||
<&clk IMX93_CLK_MIPI_CSI_GATE>,
|
||||
<&clk IMX93_CLK_MIPI_DSI_GATE>;
|
||||
clock-names = "apb", "axi", "nic", "disp", "cam",
|
||||
"pxp", "lcdif", "isi", "csi", "dsi";
|
||||
#power-domain-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg1: usb@4c100000 {
|
||||
compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x4c100000 0x200>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
|
||||
<&clk IMX93_CLK_HSIO_32K_GATE>;
|
||||
clock-names = "usb_ctrl_root_clk", "usb_wakeup";
|
||||
assigned-clocks = <&clk IMX93_CLK_HSIO>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
||||
assigned-clock-rates = <133000000>;
|
||||
phys = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc1: usbmisc@4c100200 {
|
||||
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
|
||||
"fsl,imx6q-usbmisc";
|
||||
reg = <0x4c100200 0x200>;
|
||||
#index-cells = <1>;
|
||||
};
|
||||
|
||||
usbotg2: usb@4c200000 {
|
||||
compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
|
||||
reg = <0x4c200000 0x200>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
|
||||
<&clk IMX93_CLK_HSIO_32K_GATE>;
|
||||
clock-names = "usb_ctrl_root_clk", "usb_wakeup";
|
||||
assigned-clocks = <&clk IMX93_CLK_HSIO>;
|
||||
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
||||
assigned-clock-rates = <133000000>;
|
||||
phys = <&usbphynop2>;
|
||||
fsl,usbmisc = <&usbmisc2 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc2: usbmisc@4c200200 {
|
||||
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
|
||||
"fsl,imx6q-usbmisc";
|
||||
reg = <0x4c200200 0x200>;
|
||||
#index-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -121,6 +121,7 @@ config TARGET_IMX93_VAR_SOM
|
||||
bool "imx93_var_som"
|
||||
select IMX93
|
||||
select IMX9_LPDDR4X
|
||||
imply OF_UPSTREAM
|
||||
|
||||
config TARGET_KONTRON_MX93
|
||||
bool "Kontron OSM-S/BL i.MX93"
|
||||
|
||||
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_OFFSET=0x700000
|
||||
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-var-som-symphony"
|
||||
CONFIG_AHAB_BOOT=y
|
||||
CONFIG_TARGET_IMX93_VAR_SOM=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
|
||||
Reference in New Issue
Block a user