#ifndef INSTRUCTION_H
#define INSTRUCTION_H

/* RISC-V RV32 I Base Instruction Set */
#define OPCODE_LUI 0x37
#define OPCODE_AUIPC 0x17
#define OPCODE_JAL 0x6F
#define OPCODE_JALR 0x67
#define OPCODE_BRANCH 0x63
#define OPCODE_LOAD 0x3
#define OPCODE_STORE 0x23
#define OPCODE_ARITHLOG_IMM 0x13
#define OPCODE_ARITHLOG 0x33
#define OPCODE_NOP 0xF
#define OPCODE_SYSTEM 0x73

/* RISC-V RV32 A Extension */
#define OPCODE_ATOMIC 0x2F

/* OPCODE_ATOMIC sub functions (func3 + func7) */
#define FUNC3_ATOMIC 0x2
#define FUNC75_LRW 0x2
#define FUNC75_SCW 0x3
#define FUNC75_AMOSWAPW 0x1
#define FUNC75_AMOADDW 0x0
#define FUNC75_AMOXORW 0x4
#define FUNC75_AMOANDW 0xC
#define FUNC75_AMOORW 0x8
#define FUNC75_AMOMINW 0x10
#define FUNC75_AMOMAXW 0x14
#define FUNC75_AMOMINUW 0x18
#define FUNC75_AMOMAXUW 0x1C

/* OPCODE_BRANCH sub functions (func3) */
#define FUNC3_BEQ 0x0
#define FUNC3_BNE 0x1
#define FUNC3_BLT 0x4
#define FUNC3_BGE 0x5
#define FUNC3_BLTU 0x6
#define FUNC3_BGEU 0x7

/* OPCODE_LOAD sub functions (func3) */
#define FUNC3_LB 0x0
#define FUNC3_LH 0x1
#define FUNC3_LW 0x2
#define FUNC3_LBU 0x4
#define FUNC3_LHU 0x5

/* OPCODE_STORE sub functions (func3) */
#define FUNC3_SB 0x0
#define FUNC3_SH 0x1
#define FUNC3_SW 0x2

/* OPCODE_ARITHLOG_IMM sub functions (func3 + func7) */
#define FUNC3_ADDI 0x0
#define FUNC3_SLTI 0x2
#define FUNC3_SLTIU 0x3
#define FUNC3_XORI 0x4
#define FUNC3_ORI 0x6
#define FUNC3_ANDI 0x7
#define FUNC3_SLLI 0x1
#define FUNC3_SRLI_SRAI 0x5
#define FUNC7_SRLI 0x0
#define FUNC7_SRAI 0x20

/* OPCODE_ARITHLOG sub functions (func3 + func7) */
#define FUNC3_ADD_SUB_MUL 0x0
#define FUNC7_ADD 0x0
#define FUNC7_SUB 0x20
#define FUNC3_SLL_MULH 0x1
#define FUNC7_SLL 0x0
#define FUNC3_SLT_MULHSU 0x2
#define FUNC7_SLT 0x0
#define FUNC3_SLTU_MULHU 0x3
#define FUNC7_SLTU 0x0
#define FUNC3_XOR_DIV 0x4
#define FUNC7_XOR 0x0
#define FUNC3_SRL_SRA_DIVU 0x5
#define FUNC7_SRL 0x0
#define FUNC7_SRA 0x20
#define FUNC3_OR_REM 0x6
#define FUNC7_OR 0x0
#define FUNC3_AND_REMU 0x7
#define FUNC7_AND 0x0
/* RISC-V RV32 M Extension */
#define FUNC7_MUL 0x1
#define FUNC7_MULH 0x1
#define FUNC7_MULHSU 0x1
#define FUNC7_MULHU 0x1
#define FUNC7_DIV 0x1
#define FUNC7_DIVU 0x1
#define FUNC7_REM 0x1
#define FUNC7_REMU 0x1

/* OPCODE_SYSTEM sub functions (func3 + imm) */
#define FUNC3_ECALL_EBREAK 0x0
#define IMM_ECALL 0x0
#define IMM_EBREAK 0x1
/* RISC-V Privileged Instructions */
#define IMM_SRET 0x102
#define IMM_MRET 0x302
#define FUNC7_SFENCEVMA 0x9
#define FUNC7_WFI 0x8
#define FUNC7_SINVALVMA 0x11
#define FUNC7_SFENCEWINVAL_SFENCEINVALIR 0xC
#define IMM5_SFENCEWINVAL 0x0
#define IMM5_SFENCEINVALIR 0x1
/* RISC-V RV32 ZICSR Extension */
#define FUNC3_CSRRW 0x1
#define FUNC3_CSRRS 0x2
#define FUNC3_CSRRC 0x3
#define FUNC3_CSRRWI 0x5
#define FUNC3_CSRRSI 0x6
#define FUNC3_CSRRCI 0x7

#endif