/dts-v1/;
/ {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "riscv-virtio";
    model = "riscv-virtio,qemu";

    chosen {
        bootargs = "debug keep_bootcon earlycon=sbi console=sbi";
        stdout-path = "/uart0@3000000";
    };

    cpus {
        #address-cells = <1>;
        #size-cells = <0>;
        timebase-frequency = <10000000>;

        cpu0: cpu@0 {
            device_type = "cpu";
            reg = <0>;
            compatible = "riscv";
            riscv,isa = "riscv,sv32";
            clock-frequency = <10000000>;
            cpu0_intc: interrupt-controller {
                #interrupt-cells = <1>;
                compatible = "riscv,cpu-intc";
                interrupt-controller;
            };
        };
    };

    ram: memory@0 {
        device_type = "memory";
        reg = <0x0 0xFFFFFFFF>;
    };

    soc {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "simple-bus";
        ranges;

        clint0: clint@2000000 {
            #interrupt-cells = <1>;
            compatible = "riscv,clint0";
            reg = <0x2000000 0xC000>;
            interrupts-extended =  <&cpu0_intc 3 &cpu0_intc 7>;
        };

        // /* FIXME: This is probably not correct for now */
        plic0: interrupt-controller@c000000 {
            #interrupt-cells = <1>;
            interrupt-controller;
            compatible = "riscv,plic0";
            reg = <0xC000000 0x4000000>;
            interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>;
            riscv,ndev = <1>;
            riscv,max-priority = <7>;
        };

        // uart0: serial@3000000 {
        //     interrupts = <0xa>;
        //     interrupt-parent = <&plic0>;
        //     clock-frequency = <0x384000>;
        //     reg = <0x3000000 0x1>;
        //     compatible = "simple-uart";
        // };
    };
    uart0: serial@3000000 {
        clock-frequency = <0x384000>;
        reg = <0x3000000 0x1>;
        compatible = "sifive,uart0";
    };
};