diff --git a/src/cpu/rv32cpu.c b/src/cpu/rv32cpu.c
index db1be6e..2dd03d8 100644
--- a/src/cpu/rv32cpu.c
+++ b/src/cpu/rv32cpu.c
@@ -556,7 +556,9 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction)
 					cpu->csr[instruction->immediate] |= cpu->regs.x[instruction->rs1];
 					break;
 				case FUNC3_CSRRC:
-					fprintf(stderr, "CSRRC\n");
+					// CSR atomic Read and Clear bits
+					cpu->regs.x[instruction->rd] = cpu->csr[instruction->immediate];
+					cpu->csr[instruction->immediate] &= (~cpu->regs.x[instruction->rs1]);
 					break;
 				case FUNC3_CSRRWI:
 					// CSR atomic Read/Write Immediate (immediate in rs1)
@@ -568,7 +570,9 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction)
 					fprintf(stderr, "CSRRSI\n");
 					break;
 				case FUNC3_CSRRCI:
-					fprintf(stderr, "CSRRCI\n");
+					// CSR atomic Read and Clear bits Immediate (immediate in rs1)
+					cpu->regs.x[instruction->rd] = cpu->csr[instruction->immediate];
+					cpu->csr[instruction->immediate] &= (~((uint32_t) instruction->rs1));
 					break;
 				default:
 					fprintf(stderr, "FATAL: Unknown func3 0x%x for SYSTEM instruction while executing\n", instruction->func3);