diff --git a/src/cpu/rv32cpu.c b/src/cpu/rv32cpu.c
index a917c05..5f1338d 100644
--- a/src/cpu/rv32cpu.c
+++ b/src/cpu/rv32cpu.c
@@ -71,7 +71,7 @@ static void cpu_decode(raw_instruction_t raw_instruction, instruction_t* output)
 			// Then following 10 bits (30-21) are immediate bits 10-1
 			output->immediate |= (raw_instruction.data & 0x7FE00000) >> 20;
 			// Following bit (20) is immediate bit 11
-			output->immediate |= (raw_instruction.data & 0x200000) >> 9;
+			output->immediate |= (raw_instruction.data & 0x100000) >> 9;
 			// Last bits (19-12) are immediate bits 19-12
 			output->immediate |= (raw_instruction.data & 0xFF000);
 			break;
@@ -722,7 +722,7 @@ static void cpu_print_instruction(instruction_t* instruction)
 			// Jump And Link
 			// Sign extend immediate from 21 bits to 32 bits
 			uint32_t immediate = (instruction->immediate & 0x1FFFFF) | (instruction->immediate & 0x100000 ? 0xFFE00000 : 0);
-			printf("jal x%u, 0x%x\n", instruction->rd, immediate);
+			printf("jal x%u, %d (=0x%x)\n", instruction->rd, immediate, immediate);
 			break;
 		}
 		case OPCODE_JALR:
@@ -733,7 +733,7 @@ static void cpu_print_instruction(instruction_t* instruction)
 			if(immediate == 0x0 && instruction->rd == 0 && instruction->rs1 == 1)
 				printf("ret\n");
 			else
-				printf("jalr x%u, x%u, 0x%x\n", instruction->rd, instruction->rs1, immediate);
+				printf("jalr x%u, %d(x%u)\n", instruction->rd, immediate, instruction->rs1);
 			break;
 		}
 		case OPCODE_BRANCH: