From 13f7f21b49ad0a326bee4f6f811e3aa0db54f001 Mon Sep 17 00:00:00 2001
From: vhaudiquet <vhaudiquet343@hotmail.fr>
Date: Tue, 10 Oct 2023 11:06:53 +0200
Subject: [PATCH] Added CSRRW/CSRRS basic support For now we allow all
 write/read in all CSR (just an array)

---
 src/cpu/csr.h     | 38 ++++++++++++++++++++++++++++++++++++++
 src/cpu/rv32cpu.c | 10 ++++++++--
 src/cpu/rv32cpu.h |  3 +++
 3 files changed, 49 insertions(+), 2 deletions(-)
 create mode 100644 src/cpu/csr.h

diff --git a/src/cpu/csr.h b/src/cpu/csr.h
new file mode 100644
index 0000000..0c8ab52
--- /dev/null
+++ b/src/cpu/csr.h
@@ -0,0 +1,38 @@
+#ifndef CSR_H
+#define CSR_H
+
+/* ZICSR : Control and Status Registers */
+#define CSR_COUNT 0x2000
+
+/* Machine-level CSR */
+#define CSR_MVENDORID 0xF11
+#define CSR_MARCHID 0xF12
+#define CSR_MIMPID 0xF13
+#define CSR_MHARTID 0xF14
+#define CSR_MCONFIGPTR 0xF15
+/* Machine Trap setup CSR */
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSTATUSH 0x310
+/* Machine Trap handling CSR */
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+#define CSR_MTINST 0x34A
+#define CSR_MTVAL2 0x34B
+/* Machine Configuration */
+#define CSR_MENVCFG 0x30A
+#define CSR_MENVCFGH 0x31A
+#define CSR_MSECCFG 0x747
+#define CSR_MSECCFGH 0x757
+/* Machine Memory Protection */
+#define CSR_PMPCFG0 0x3A0
+
+#endif
diff --git a/src/cpu/rv32cpu.c b/src/cpu/rv32cpu.c
index 0d4eb2b..cc09dc8 100644
--- a/src/cpu/rv32cpu.c
+++ b/src/cpu/rv32cpu.c
@@ -1,5 +1,6 @@
 #include "rv32cpu.h"
 #include "instruction.h"
+#include "csr.h"
 
 #include "memory/memory.h"
 #include "memory/mmu/mmu.h"
@@ -535,10 +536,15 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction)
 					}
 					break;
 				case FUNC3_CSRRW:
-					fprintf(stderr, "CSRRW\n");
+					// CSR atomic Read/Write
+					uint32_t csrrw_old_value = cpu->csr[instruction->immediate];
+					cpu->csr[instruction->immediate] = cpu->regs.x[instruction->rs1];
+					cpu->regs.x[instruction->rd] = csrrw_old_value;
 					break;
 				case FUNC3_CSRRS:
-					fprintf(stderr, "CSRRS\n");
+					// CSR atomic Read and Set bits
+					cpu->regs.x[instruction->rd] = cpu->csr[instruction->immediate];
+					cpu->csr[instruction->immediate] |= cpu->regs.x[instruction->rs1];
 					break;
 				case FUNC3_CSRRC:
 					fprintf(stderr, "CSRRC\n");
diff --git a/src/cpu/rv32cpu.h b/src/cpu/rv32cpu.h
index 01465a9..06f2a0f 100644
--- a/src/cpu/rv32cpu.h
+++ b/src/cpu/rv32cpu.h
@@ -5,6 +5,8 @@
 #include <pthread.h>
 #include <stdlib.h>
 
+#include "csr.h"
+
 /*
 * This is a structure encoding for the registers of
 * the rv32 cpu.
@@ -188,6 +190,7 @@ typedef struct RV32_CPU
 	// CPU values
     rv32_cpu_regs_t regs;
     uint32_t pc;
+	uint32_t csr[CSR_COUNT];
 
 	// Simulation data
 	ssize_t sim_ticks_left; // -1 : simulate forever