Tom Rini
8c212d6e2e
The U_BOOT_DRIVER macro creates a list of drivers used at link time, and all entries here must be unique. This in turn means that all entries in the code should also be unique in order to not lead to build failures later with unexpected build combinations. Typically, the problem we have here is when a driver is obviously based on another driver and didn't update this particular field and so while the name field reflects something unique the linker entry itself is not. In a few places this provides a more suitable string name as well, however. Reviewed-by: Marek Vasut <marek.vasut+usb@mailbox.org> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # Tegra Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Heiko Schocher <hs@nabladev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
88 lines
1.9 KiB
C
88 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Pepperl+Fuchs
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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* Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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*/
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#include <command.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <sysreset.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/secure.h>
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#define GICD_CTRL_ADDRESS 0xfffc1000
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static __always_inline void __l2_reset_cpu(void)
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{
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asm volatile(/* Disable GIC distributor (IRQs). */
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"str wzr, [%3]\n"
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/* Set Magic Number */
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"str %0, [%1]\n"
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/* Increase timeout in rstmgr.hdsktimeout */
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"ldr x2, =0xFFFFFF\n"
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"str w2, [%2, #0x64]\n"
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"ldr w2, [%2, #0x10]\n"
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/*
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* Set l2flushen = 1, etrstallen = 1,
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* fpgahsen = 1 and sdrselfrefen = 1
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* in rstmgr.hdsken to perform handshake
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* in certain peripherals before trigger
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* L2 reset.
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*/
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"ldr x3, =0x10D\n"
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"orr x2, x2, x3\n"
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"str w2, [%2, #0x10]\n"
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/* Trigger L2 reset in rstmgr.coldmodrst */
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"ldr w2, [%2, #0x34]\n"
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"orr x2, x2, #0x100\n"
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"isb\n"
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"dsb sy\n"
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"str w2, [%2, #0x34]\n"
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/* Put all cores into WFI mode */
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"1:\n"
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" wfi\n"
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" b 1b\n"
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: : "r" (L2_RESET_DONE_STATUS),
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"r" (L2_RESET_DONE_REG),
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"r" (SOCFPGA_RSTMGR_ADDRESS),
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"r" (GICD_CTRL_ADDRESS)
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: "x1", "x2", "x3");
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}
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static void l2_reset_cpu(void)
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{
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__l2_reset_cpu();
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}
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static int socfpga_sysreset_request(struct udevice *dev,
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enum sysreset_t type)
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{
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if (type == SYSRESET_WARM) {
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/* flush dcache */
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flush_dcache_all();
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/* request a warm reset */
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puts("Do warm reset now...\n");
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l2_reset_cpu();
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} else {
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puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
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mbox_reset_cold();
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}
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return -EINPROGRESS;
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}
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static struct sysreset_ops socfpga_sysreset = {
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.request = socfpga_sysreset_request,
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};
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U_BOOT_DRIVER(sysreset_socfpga_soc64) = {
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.id = UCLASS_SYSRESET,
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.name = "socfpga_sysreset",
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.ops = &socfpga_sysreset,
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};
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