Marek VasutandTom Rini
d504639843
Set the acpi_ops structure as static const where applicable. The The structure is not accessible from outside of drivers and is not going to be modified at runtime. The structure may be unused in a couple of drivers depending on their configuration, mark those sites with __maybe_unused . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Simon Glass <sjg@chromium.org>
152 lines
3.2 KiB
C
152 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 9elements GmbH
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*/
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#include <cpu.h>
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#include <dm.h>
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#include <irq.h>
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#include <acpi/acpigen.h>
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#include <asm/armv8/cpu.h>
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#include <asm/io.h>
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#include <dm/acpi.h>
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#include <linux/bitops.h>
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#include <linux/printk.h>
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#include <linux/sizes.h>
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static int armv8_cpu_get_desc(const struct udevice *dev, char *buf, int size)
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{
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int cpuid;
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cpuid = (read_midr() & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT;
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snprintf(buf, size, "CPU MIDR %04x", cpuid);
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return 0;
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}
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static int armv8_cpu_get_info(const struct udevice *dev,
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struct cpu_info *info)
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{
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info->cpu_freq = 0;
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info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
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return 0;
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}
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static int armv8_cpu_get_count(const struct udevice *dev)
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{
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return uclass_id_count(UCLASS_CPU);
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}
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#ifdef CONFIG_ACPIGEN
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int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
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{
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uint core_id = dev_seq(dev);
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acpigen_write_processor_device(ctx, core_id);
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return 0;
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}
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int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
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{
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struct acpi_madt_gicc *gicc;
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struct cpu_plat *cpu_plat;
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struct udevice *gic;
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u64 gicc_gicv = 0;
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u64 gicc_gich = 0;
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u64 gicc_gicr_base = 0;
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u64 gicc_phys_base = 0;
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u32 gicc_perf_gsiv = 0;
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u64 gicc_mpidr;
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u32 gicc_vgic_maint_irq = 0;
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int addr_index;
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fdt_addr_t addr;
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int ret;
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struct irq req_irq;
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cpu_plat = dev_get_parent_plat(dev);
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if (!cpu_plat)
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return 0;
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ret = irq_get_interrupt_parent(dev, &gic);
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if (ret) {
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log_err("%s: Failed to find interrupt parent for %s\n",
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__func__, dev->name);
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return -ENODEV;
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}
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addr_index = 1;
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if (device_is_compatible(gic, "arm,gic-v3")) {
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addr = dev_read_addr_index(gic, addr_index++);
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if (addr != FDT_ADDR_T_NONE)
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gicc_gicr_base = addr;
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}
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addr = dev_read_addr_index(gic, addr_index++);
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if (addr != FDT_ADDR_T_NONE)
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gicc_phys_base = addr;
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addr = dev_read_addr_index(gic, addr_index++);
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if (addr != FDT_ADDR_T_NONE)
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gicc_gich = addr;
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addr = dev_read_addr_index(gic, addr_index++);
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if (addr != FDT_ADDR_T_NONE)
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gicc_gicv = addr;
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ret = irq_get_by_index(gic, 0, &req_irq);
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if (!ret)
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gicc_vgic_maint_irq = req_irq.id;
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gicc_mpidr = dev_read_u64_default(dev, "reg", 0);
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if (!gicc_mpidr)
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gicc_mpidr = dev_read_u32_default(dev, "reg", 0);
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/*
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* gicc_vgic_maint_irq and gicc_gicv are the same for every CPU
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*/
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gicc = ctx->current;
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acpi_write_madt_gicc(gicc,
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dev_seq(dev),
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gicc_perf_gsiv, /* FIXME: needs a PMU driver */
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gicc_phys_base,
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gicc_gicv,
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gicc_gich,
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gicc_vgic_maint_irq,
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gicc_gicr_base,
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gicc_mpidr,
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0); /* FIXME: Not defined in DT */
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acpi_inc(ctx, gicc->length);
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return 0;
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}
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static const struct acpi_ops armv8_cpu_acpi_ops = {
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.fill_ssdt = armv8_cpu_fill_ssdt,
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.fill_madt = armv8_cpu_fill_madt,
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};
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#endif
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static const struct cpu_ops cpu_ops = {
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.get_count = armv8_cpu_get_count,
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.get_desc = armv8_cpu_get_desc,
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.get_info = armv8_cpu_get_info,
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};
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static const struct udevice_id cpu_ids[] = {
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{ .compatible = "arm,armv8" },
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{}
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};
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U_BOOT_DRIVER(arm_cpu) = {
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.name = "arm-cpu",
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.id = UCLASS_CPU,
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.of_match = cpu_ids,
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.ops = &cpu_ops,
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.flags = DM_FLAG_PRE_RELOC,
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ACPI_OPS_PTR(&armv8_cpu_acpi_ops)
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};
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