Padmarao BegariandMichal Simek
a5f2aa4b38
The clock driver fails to correctly calculate the PLL clock rate for peripherals when using the DPLL as the clock source. The DPLL operates within the full power domain, while peripheral clocks reside in the low power domain. To ensure accurate PLL clock rate computation when the peripheral clock source is set to DPLL, the DPLL-to-LPD cross divisor is used. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Link: https://lore.kernel.org/r/20250618094329.296731-1-padmarao.begari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>