Michal Simek
9e8a0f54b0
Move the controller/PHY reset and SRAM-bypass sequence from hce_enable_notify(PRE_CHANGE) into ufs_versal2_init(). The reset sequence releases the host controller from reset, and the UFS core reads the capability and version registers right after .init() and before ufshcd_hba_enable() (the only caller of hce_enable_notify()). Doing the reset in .init() ensures those registers are read after the controller is out of reset, and keeps the driver aligned with Linux. ufs_versal2_phy_init() stays in POST_CHANGE. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://patch.msgid.link/6b4cbfa6cc58bef86da86971e4b27726a4e510f0.1785394153.git.michal.simek@amd.com