Add a driver for the MT8183 MIPI DSI host controller (DSI0). It
implements the DSI_HOST uclass: init() brings up the clock gates, the
external MIPI TX D-PHY (through the generic PHY API), the D-PHY
timing registers and the video mode timing, and enable() switches the
host to video mode and starts the stream, so that panel
initialization can be performed over the command FIFO in between.
The register map and the D-PHY timing computation are ported from the
Linux kernel driver drivers/gpu/drm/mediatek/mtk_dsi.c; the video mode
timing computation (including the D-PHY turnaround adjustment taken
out of the horizontal porch) and the command queue programming follow
the ChromeOS coreboot port src/soc/mediatek/common/dsi.c, which is
proven to drive this controller on the kukui family of boards.
DSI transfers are performed through the command queue in low power
mode for panels that request it and high speed otherwise, with bus
turn-around and receive support for read commands. The panel child
node of the DSI controller is bound from the bind() hook.
Signed-off-by: Vincent Haudiquet <vhaudiquet@gmail.com>
Vincent Haudiquet
3bb613ee2f