Danish Ahmad RosdiandMichal Simek 7edbbfca63 drivers: fpga: Use FPGA_INTEL_SDM_MAILBOX conditional instead of Agilex/Stratix10 ...

Replace the conditional compilation checks for
CONFIG_ARCH_SOCFPGA_AGILEX and CONFIG_ARCH_SOCFPGA_STRATIX10 with
CONFIG_FPGA_INTEL_SDM_MAILBOX.

Signed-off-by: Danish Ahmad Rosdi <danish.ahmad.rosdi@altera.com>
Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260608094547.3026-1-chen.huei.lok@altera.com

2026-07-08 08:55:51 +02:00

..

altera.c

drivers: fpga: Use FPGA_INTEL_SDM_MAILBOX conditional instead of Agilex/Stratix10

2026-07-08 08:55:51 +02:00

cyclon2.c

fpga: cyclon2: Remove message never printed

2025-08-25 16:20:47 +02:00

fpga-uclass.c

…

fpga.c

fpga: lattice: Remove unused support

2025-08-25 16:20:48 +02:00

intel_sdm_mb.c

…

Kconfig

Replace TARGET namespace and cleanup properly

2026-02-14 11:06:46 -06:00

Makefile

Replace TARGET namespace and cleanup properly

2026-02-14 11:06:46 -06:00

sandbox.c

…

socfpga_arria10.c

…

socfpga_gen5.c

…

socfpga.c

…

spartan2.c

treewide: prefer __func__ over __FUNCTION__ and __PRETTY_FUNCTION__

2026-06-10 14:49:46 -06:00

spartan3.c

treewide: prefer __func__ over __FUNCTION__ and __PRETTY_FUNCTION__

2026-06-10 14:49:46 -06:00

stratixII.c

…

stratixv.c

…

versalpl.c

fpga: versalpl: Fix unaligned buffer handling

2026-05-25 15:14:05 +02:00

virtex2.c

…

xilinx.c

treewide: prefer __func__ over __FUNCTION__ and __PRETTY_FUNCTION__

2026-06-10 14:49:46 -06:00

zynqmppl.c

drivers: firmware: update xilinx_pm_request to support max payload

2025-10-09 09:07:03 +02:00

zynqpl.c

…