Marek VasutandHeinrich Schuchardt
dc3765ede5
The "env" command is the recommended environment management command, its "set" subcommand is the equivalent replacement for legacy "setenv" command. Update the documentation to use the contemporary "env set" command instead of legacy "setenv" command. Note that the "setenv" command is unlikely to be removed from U-Boot in the near future due to it being integral part of the command line ABI. Implemented using: $ sed -i 's@\<setenv\>@env set@g' $(git grep -li '\<setenv\>' doc/) README Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
440 lines
21 KiB
Plaintext
440 lines
21 KiB
Plaintext
Table of interleaving 2-4 controllers
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=====================================
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+--------------+-----------------------------------------------------------+
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|Configuration | Memory Controller |
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| | 1 2 3 4 |
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|--------------+--------------+--------------+-----------------------------+
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| Two memory | Not Intlv'ed | Not Intlv'ed | |
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| complexes +--------------+--------------+ |
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| | 2-way Intlv'ed | |
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|--------------+--------------+--------------+--------------+ |
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| | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
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| Three memory +--------------+--------------+--------------+ |
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| complexes | 2-way Intlv'ed | Not Intlv'ed | |
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| +-----------------------------+--------------+ |
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| | 3-way Intlv'ed | |
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+--------------+--------------+--------------+--------------+--------------+
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| | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
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| Four memory +--------------+--------------+--------------+--------------+
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| complexes | 2-way Intlv'ed | 2-way Intlv'ed |
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| +-----------------------------+-----------------------------+
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| | 4-way Intlv'ed |
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+--------------+-----------------------------------------------------------+
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Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
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======================================================
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+-------------+---------------------------------------------------------+
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| | Rank Interleaving |
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| +--------+-----------+-----------+------------+-----------+
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|Memory | | | | 2x2 | 4x1 |
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|Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
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|Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
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+-------------+--------+-----------+-----------+------------+-----------+
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|None | Yes | Yes | Yes | Yes | Yes |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Cacheline | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Page | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Bank | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Superbank | No | Yes | No | No, Only(*)| Yes |
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| | | | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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(*) Although the hardware can be configured with memory controller
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interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
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from each controller. {CS2+CS3} on each controller are only rank
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interleaved on that controller.
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For memory controller interleaving, identical DIMMs are suggested. Software
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doesn't check the size or organization of interleaved DIMMs.
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The ways to configure the ddr interleaving mode
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==============================================
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1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
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under "CFG_EXTRA_ENV_SETTINGS", like:
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#define CFG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=bank" \
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......
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2. Run U-Boot "env set" command to configure the memory interleaving mode.
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Either numerical or string value is accepted.
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# disable memory controller interleaving
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env set hwconfig "fsl_ddr:ctlr_intlv=null"
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# cacheline interleaving
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env set hwconfig "fsl_ddr:ctlr_intlv=cacheline"
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# page interleaving
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env set hwconfig "fsl_ddr:ctlr_intlv=page"
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# bank interleaving
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env set hwconfig "fsl_ddr:ctlr_intlv=bank"
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# superbank
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env set hwconfig "fsl_ddr:ctlr_intlv=superbank"
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# 1KB 3-way interleaving
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env set hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
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# 4KB 3-way interleaving
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env set hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
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# 8KB 3-way interleaving
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env set hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
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# disable bank (chip-select) interleaving
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env set hwconfig "fsl_ddr:bank_intlv=null"
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# bank(chip-select) interleaving cs0+cs1
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env set hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
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# bank(chip-select) interleaving cs2+cs3
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env set hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
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# bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
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env set hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
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# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
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env set hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
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# bank(chip-select) interleaving (auto)
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env set hwconfig "fsl_ddr:bank_intlv=auto"
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This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
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on DIMMs.
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Memory controller address hashing
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==================================
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If the DDR controller supports address hashing, it can be enabled by hwconfig.
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Syntax is:
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hwconfig=fsl_ddr:addr_hash=true
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Memory controller ECC on/off
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============================
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If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
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ECC can be turned on/off by hwconfig.
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Syntax is
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hwconfig=fsl_ddr:ecc=off
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Memory address parity on/off
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============================
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address parity can be turned on/off by hwconfig.
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Syntax is:
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hwconfig=fsl_ddr:parity=on
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Memory testing options for mpc85xx
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==================================
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1. Memory test can be done once U-Boot prompt comes up using mtest, or
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2. Memory test can be done with Power-On-Self-Test function, activated at
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compile time.
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In order to enable the POST memory test, CFG_POST needs to be
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defined in board configuraiton header file. By default, POST memory test
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performs a fast test. A slow test can be enabled by changing the flag at
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compiling time. To test memory bigger than 2GB, 36BIT support is needed.
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Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
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window to physical address so that all physical memory can be tested.
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Combination of hwconfig
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=======================
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Hwconfig can be combined with multiple parameters, for example, on a supported
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platform
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hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
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Table for dynamic ODT for DDR3
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==============================
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For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
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be needed, depending on the configuration. The numbers in the following tables are
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in Ohms.
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* denotes dynamic ODT
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Two slots system
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+-----------------------+----------+---------------+-----------------------------+-----------------------------+
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| Configuration | |DRAM controller| Slot 1 | Slot 2 |
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+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
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| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
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+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
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| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
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| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
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| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
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|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
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|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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Single slot system
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+-------------+------------+---------------+-----------------------------+-----------------------------+
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| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
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|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
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+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
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| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
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| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
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| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
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+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R1 | off | 75 | 40 | off | off | off |
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| Dual Rank |------------+-------+-------+-------+------+-------+------+
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| | R2 | off | 75 | 40 | off | off | off |
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+-------------+------------+-------+-------+-------+------+-------+------+
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| Single Rank | R1 | off | 75 | 40 | off |
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+-------------+------------+-------+-------+-------+------+
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Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
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http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
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Table for ODT for DDR2
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======================
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Two slots system
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+-----------------------+----------+---------------+-----------------------------+-----------------------------+
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| Configuration | |DRAM controller| Slot 1 | Slot 2 |
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+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
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| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
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+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
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| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off |
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| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | |
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| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off |
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|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | |
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|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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|Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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Single slot system
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+-------------+------------+---------------+-----------------------------+
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| | |DRAM controller| Rank 1 | Rank 2 |
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|Configuration| Write/Read |-------+-------+-------+------+-------+------+
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| | | Write | Read | Write | Read | Write | Read |
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+-------------+------------+-------+-------+-------+------+-------+------+
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| | R1 | off | 75 | 150 | off | off | off |
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| Dual Rank |------------+-------+-------+-------+------+-------+------+
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| | R2 | off | 75 | 150 | off | off | off |
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+-------------+------------+-------+-------+-------+------+-------+------+
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| Single Rank | R1 | off | 75 | 150 | off |
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+-------------+------------+-------+-------+-------+------+
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Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
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Interactive DDR debugging
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===========================
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For DDR parameter tuning up and debugging, the interactive DDR debugger can
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be activated by setting the environment variable "ddr_interactive" to any
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value. (The value of ddr_interactive may have a meaning in the future, but,
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for now, the presence of the variable will cause the debugger to run.) Once
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activated, U-Boot will show the prompt "FSL DDR>" before enabling the DDR
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controller. The available commands are printed by typing "help".
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Another way to enter the interactive DDR debugger without setting the
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environment variable is to send the 'd' character early during the boot
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process. To save booting time, no additional delay is added, so the window
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to send the key press is very short -- basically, it is the time before the
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memory controller code starts to run. For example, when rebooting from
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within U-Boot, the user must press 'd' IMMEDIATELY after hitting enter to
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initiate a 'reset' command. In case of power on/reset, the user can hold
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down the 'd' key while applying power or hitting the board's reset button.
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The example flow of using interactive debugging is
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type command "compute" to calculate the parameters from the default
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type command "print" with arguments to show SPD, options, registers
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type command "edit" with arguments to change any if desired
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type command "copy" with arguments to copy controller/dimm settings
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type command "go" to continue calculation and enable DDR controller
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Additional commands to restart the debugging are:
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type command "reset" to reset the board
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type command "recompute" to reload SPD and start over
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Note, check "next_step" to show the flow. For example, after edit opts, the
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next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
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STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the
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DDR controller with the current setting without further calculation and then
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exit to resume the booting of the machine.
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The detail syntax for each commands are
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print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
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c<n> - the controller number, eg. c0, c1
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d<n> - the DIMM number, eg. d0, d1
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spd - print SPD data
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dimmparms - DIMM parameters, calculated from SPD
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commonparms - lowest common parameters for all DIMMs
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opts - options
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addresses - address assignment (not implemented yet)
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regs - controller registers
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edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
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c<n> - the controller number, eg. c0, c1
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d<n> - the DIMM number, eg. d0, d1
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spd - print SPD data
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dimmparms - DIMM parameters, calculated from SPD
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commonparms - lowest common parameters for all DIMMs
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opts - options
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addresses - address assignment (not implemented yet)
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regs - controller registers
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<element> - name of the modified element
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byte number if the object is SPD
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<value> - decimal or heximal (prefixed with 0x) numbers
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copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
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same as for "edit" command
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DIMM numbers ignored for commonparms, opts, and regs
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reset
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no arguement - reset the board
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recompute
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no argument - reload SPD and start over
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compute
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no argument - recompute from current next_step
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next_step
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no argument - show current next_step
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help
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no argument - print a list of all commands
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go
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no argument - program memory controller(s) and continue with U-Boot
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Examples of debugging flow
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FSL DDR>compute
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Detected UDIMM UG51U6400N8SU-ACF
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FSL DDR>print
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print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
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FSL DDR>print dimmparms
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DIMM parameters: Controller=0 DIMM=0
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DIMM organization parameters:
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module part name = UG51U6400N8SU-ACF
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rank_density = 2147483648 bytes (2048 megabytes)
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capacity = 4294967296 bytes (4096 megabytes)
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burst_lengths_bitmask = 0C
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base_addresss = 0 (00000000 00000000)
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n_ranks = 2
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data_width = 64
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primary_sdram_width = 64
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ec_sdram_width = 0
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registered_dimm = 0
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n_row_addr = 15
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n_col_addr = 10
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edc_config = 0
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n_banks_per_sdram_device = 8
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tCKmin_X_ps = 1500
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tCKmin_X_minus_1_ps = 0
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tCKmin_X_minus_2_ps = 0
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tCKmax_ps = 0
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caslat_X = 960
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tAA_ps = 13125
|
|
caslat_X_minus_1 = 0
|
|
caslat_X_minus_2 = 0
|
|
caslat_lowest_derated = 0
|
|
tRCD_ps = 13125
|
|
tRP_ps = 13125
|
|
tRAS_ps = 36000
|
|
tWR_ps = 15000
|
|
tWTR_ps = 7500
|
|
tRFC_ps = 160000
|
|
tRRD_ps = 6000
|
|
tRC_ps = 49125
|
|
refresh_rate_ps = 7800000
|
|
tIS_ps = 0
|
|
tIH_ps = 0
|
|
tDS_ps = 0
|
|
tDH_ps = 0
|
|
tRTP_ps = 7500
|
|
tDQSQ_max_ps = 0
|
|
tQHS_ps = 0
|
|
FSL DDR>edit c0 opts ECC_mode 0
|
|
FSL DDR>edit c0 regs cs0_bnds 0x000000FF
|
|
FSL DDR>go
|
|
2 GiB left unmapped
|
|
4 GiB (DDR3, 64-bit, CL=9, ECC off)
|
|
DDR Chip-Select Interleaving Mode: CS0+CS1
|
|
Testing 0x00000000 - 0x7fffffff
|
|
Testing 0x80000000 - 0xffffffff
|
|
Remap DDR 2 GiB left unmapped
|
|
|
|
POST memory PASSED
|
|
Flash: 128 MiB
|
|
L2: 128 KB enabled
|
|
Corenet Platform Cache: 1024 KB enabled
|
|
SERDES: timeout resetting bank 3
|
|
SRIO1: disabled
|
|
SRIO2: disabled
|
|
MMC: FSL_ESDHC: 0
|
|
EEPROM: Invalid ID (ff ff ff ff)
|
|
PCIe1: disabled
|
|
PCIe2: Root Complex, x1, regs @ 0xfe201000
|
|
01:00.0 - 8086:10d3 - Network controller
|
|
PCIe2: Bus 00 - 01
|
|
PCIe3: disabled
|
|
In: serial
|
|
Out: serial
|
|
Err: serial
|
|
Net: Initializing Fman
|
|
Fman1: Uploading microcode version 101.8.0
|
|
e1000: 00:1b:21:81:d2:e0
|
|
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
|
|
Warning: e1000#0 MAC addresses don't match:
|
|
Address in SROM is 00:1b:21:81:d2:e0
|
|
Address in environment is 00:e0:0c:00:ea:05
|
|
|
|
Hit any key to stop autoboot: 0
|
|
=>
|