net: SYS_RX_ETH_BUFFER defaults to 8 when CONFIG_FSL_ENETC=y

drivers/net/fsl_enetc.h specifies ENETC_BD_CNT "buffer descriptors count
must be a multiple of 8". This constant is set to
CONFIG_SYS_RX_ETH_BUFFER which defaults to 4.

All defconfigs enabling CONFIG_FSL_ENETC fortunately have it set to 8,
according to
./tools/qconfig.py -l -f CONFIG_FSL_ENETC '~CONFIG_SYS_RX_ETH_BUFFER=8'.

Let's make sure the default is sane by having it set to 8 when this
driver is enabled. Note that originally[1] it was said EEPRO100 and 405
EMAC should be 8 or higher. 405 (PPC405?) support seems to have been
dropped in commit b5e7c84f72 ("ppc4xx: remove ASH405 board"), 11 years
ago. Maybe there's something we can do for EEPRO100 though?

Start all lines with a tab instead of spaces.

Specify limitation for FSL_ENETC in the help text.

[1] commit 53cf9435cc ("- CFG_RX_ETH_BUFFER added.")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

net/Kconfig

@@ -280,12 +280,15 @@ config TFTP_BLOCKSIZE
 	  You can also activate CONFIG_IP_DEFRAG to set a larger block.
 
 config SYS_RX_ETH_BUFFER
-        int "Number of receive packet buffers"
-        default 4
-        help
-          Defines the number of Ethernet receive buffers. On some Ethernet
-          controllers it is recommended to set this value to 8 or even higher,
-          since all buffers can be full shortly after enabling the interface on
-          high Ethernet traffic.
+	int "Number of receive packet buffers"
+	default 8 if FSL_ENETC
+	default 4
+	help
+	  Defines the number of Ethernet receive buffers. On some Ethernet
+	  controllers (e.g. FSL_ENETC) it is recommended to set this value to 8
+	  or even higher, since all buffers can be full shortly after enabling
+	  the interface on high Ethernet traffic.
+
+	  FSL_ENETC requires this value to be a multiple of 8.
 
 endif   # if NET