diff --git a/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi b/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
index 26361780c01..452bf3d41f1 100644
--- a/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
@@ -6,6 +6,21 @@
 #include "imx8mm-u-boot.dtsi"
 
 / {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * Limit memory usage below the 4 GB (32-bit) boundary.
+		 * The i.MX8MM DMA and peripherals cannot access >32-bit
+		 * addresses. This prevents allocation failures in UEFI mode.
+		 */
+		u_boot_sdma_shield: sdma-shield@100000000 {
+			reg = <0x1 0x00000000 0x0 0x40000000>;
+		};
+	};
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
@@ -29,6 +44,10 @@
 	};
 };
 
+&pinctrl_i2c1 {
+	bootph-pre-ram;
+};
+
 &pinctrl_uart3 {
 	bootph-pre-ram;
 };
@@ -73,6 +92,10 @@
 	bootph-pre-ram;
 };
 
+&i2c1 {
+	bootph-pre-ram;
+};
+
 &usdhc2 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/imx95-15x15-frdm-u-boot.dtsi b/arch/arm/dts/imx95-15x15-frdm-u-boot.dtsi
new file mode 100644
index 00000000000..aa289bd65aa
--- /dev/null
+++ b/arch/arm/dts/imx95-15x15-frdm-u-boot.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "imx95-u-boot.dtsi"
+
+/ {
+	aliases {
+		pci0 = &netc_bus0;
+		pci1 = &netc_bus1;
+	};
+};
+
+&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} {
+	filename = "lpddr4x_imem_v202409.bin";
+};
+
+&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} {
+	filename = "lpddr4x_dmem_v202409.bin";
+};
+
+&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} {
+	filename = "lpddr4x_imem_qb_v202409.bin";
+};
+
+&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} {
+	filename = "lpddr4x_dmem_qb_v202409.bin";
+};
+
+&lpuart1 {
+	bootph-pre-ram;
+};
+
+&reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+	bootph-pre-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index cbd0078ba2a..1271a3e88e6 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -165,6 +165,14 @@ config TARGET_IMX95_15X15_EVK
 	imply BOOTSTD_FULL
 	imply OF_UPSTREAM
 
+config TARGET_IMX95_15X15_FRDM
+	bool "imx95_frdm"
+	select OF_BOARD_FIXUP
+	select IMX95
+	imply BOOTSTD_FULL
+	imply BOOTSTD_BOOTCOMMAND
+	imply OF_UPSTREAM
+
 config TARGET_IMX943_EVK
 	bool "imx943_evk"
 	select OF_BOARD_FIXUP
@@ -210,6 +218,7 @@ source "board/phytec/phycore_imx91_93/Kconfig"
 source "board/variscite/imx93_var_som/Kconfig"
 source "board/nxp/imx94_evk/Kconfig"
 source "board/nxp/imx95_evk/Kconfig"
+source "board/nxp/imx95_frdm/Kconfig"
 source "board/toradex/aquila-imx95/Kconfig"
 source "board/toradex/smarc-imx95/Kconfig"
 source "board/toradex/verdin-imx95/Kconfig"
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index e8f739920be..8bb3ce5cad9 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -773,22 +773,20 @@ int get_reset_reason(bool sys, bool lm)
 		}
 
 		if (out.bootflags & MISC_BOOT_FLAG_VLD) {
-			printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n",
-			       rst[out.bootflags & MISC_BOOT_FLAG_REASON],
-			       out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
-			       FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
-			       out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
-			       FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
-			       );
+			printf("SYS Boot reason: %s", rst[out.bootflags & MISC_BOOT_FLAG_REASON]);
+			if (out.bootflags & MISC_BOOT_FLAG_ORG_VLD)
+				printf(", origin: %ld", FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags));
+			if (out.bootflags & MISC_BOOT_FLAG_ERR_VLD)
+				printf(", errid: %ld", FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags));
+			puts("\n");
 		}
 		if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
-			printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n",
-			       rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON],
-			       out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
-			       FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1,
-			       out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
-			       FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1
-			       );
+			printf("SYS shutdown reason: %s", rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON]);
+			if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD)
+				printf(", origin: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags));
+			if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD)
+				printf(", errid: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags));
+			puts("\n");
 		}
 	}
 
@@ -803,23 +801,21 @@ int get_reset_reason(bool sys, bool lm)
 		}
 
 		if (out.bootflags & MISC_BOOT_FLAG_VLD) {
-			printf("LM Boot reason: %s, origin: %ld, errid: %ld\n",
-			       rst[out.bootflags & MISC_BOOT_FLAG_REASON],
-			       out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
-			       FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
-			       out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
-			       FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
-			       );
+			printf("LM Boot reason: %s", rst[out.bootflags & MISC_BOOT_FLAG_REASON]);
+			if (out.bootflags & MISC_BOOT_FLAG_ORG_VLD)
+				printf(", origin: %ld", FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags));
+			if (out.bootflags & MISC_BOOT_FLAG_ERR_VLD)
+				printf(", errid: %ld", FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags));
+			puts("\n");
 		}
 
 		if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
-			printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n",
-			       rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON],
-			       out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
-			       FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1,
-			       out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
-			       FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1
-			       );
+			printf("LM shutdown reason: %s", rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON]);
+			if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD)
+				printf(", origin: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags));
+			if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD)
+				printf(", errid: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags));
+			puts("\n");
 		}
 	}
 
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index e504c1fd52a..8a858dea518 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -331,6 +331,12 @@ int arch_cpu_init(void)
 
 	init_snvs();
 
+	/*
+	 * imx_gpcv2_init() needs to do a delay.
+	 * Timer must be initialized before calling a delay function.
+	 */
+	timer_init();
+
 	imx_gpcv2_init();
 
 	enable_ca7_smp();
diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c
index 96fe2c7c17b..86311d0cc07 100644
--- a/arch/arm/mach-imx/syscounter.c
+++ b/arch/arm/mach-imx/syscounter.c
@@ -65,6 +65,9 @@ int timer_init(void)
 	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
 	unsigned long val, freq;
 
+	if (gd->arch.timer_rate_hz)
+		return 0;
+
 	freq = CFG_SC_TIMER_CLK;
 	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
@@ -103,8 +106,7 @@ ulong get_timer(ulong base)
 
 ulong timer_get_boot_us(void)
 {
-	if (!gd->arch.timer_rate_hz)
-		timer_init();
+	timer_init();
 
 	return tick_to_time(get_ticks());
 }
diff --git a/board/nxp/imx95_frdm/Kconfig b/board/nxp/imx95_frdm/Kconfig
new file mode 100644
index 00000000000..0da9a56adad
--- /dev/null
+++ b/board/nxp/imx95_frdm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX95_15X15_FRDM
+
+config SYS_BOARD
+	default "imx95_frdm"
+
+config SYS_VENDOR
+	default "nxp"
+
+config SYS_CONFIG_NAME
+	default "imx95_frdm"
+
+endif
diff --git a/board/nxp/imx95_frdm/MAINTAINERS b/board/nxp/imx95_frdm/MAINTAINERS
new file mode 100644
index 00000000000..33870f054e7
--- /dev/null
+++ b/board/nxp/imx95_frdm/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX95 FRDM BOARD
+M:	Joseph Guo <qijian.guo@nxp.com>
+S:	Maintained
+F:	board/nxp/imx95_frdm/
+F:	include/configs/imx95_frdm.h
+F:	configs/imx95_15x15_frdm_defconfig
diff --git a/board/nxp/imx95_frdm/Makefile b/board/nxp/imx95_frdm/Makefile
new file mode 100644
index 00000000000..6965c61a281
--- /dev/null
+++ b/board/nxp/imx95_frdm/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2026 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx95_frdm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/nxp/imx95_frdm/imx95_frdm.c b/board/nxp/imx95_frdm/imx95_frdm.c
new file mode 100644
index 00000000000..394d6fd459c
--- /dev/null
+++ b/board/nxp/imx95_frdm/imx95_frdm.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+		board_late_mmc_env_init();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *fdt)
+{
+	/* Remove nodes based on fuses. */
+	return imx9_uboot_fixup_by_fuse(fdt);
+}
+#endif
diff --git a/board/nxp/imx95_frdm/imx95_frdm.env b/board/nxp/imx95_frdm/imx95_frdm.env
new file mode 100644
index 00000000000..61fbd395645
--- /dev/null
+++ b/board/nxp/imx95_frdm/imx95_frdm.env
@@ -0,0 +1,93 @@
+sec_boot=no
+initrd_addr=0x93800000
+emmc_dev=0
+sd_dev=1
+scriptaddr=0x93500000
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+image=Image
+kernel_comp_addr_r=0xC0000000
+kernel_comp_size=0x2000000
+splashimage=0xA0000000
+console=ttyLP0,115200 earlycon
+fdt_addr_r=0x93000000
+fdt_addr=0x93000000
+cntr_addr=0xA8000000
+cntr_file=os_cntr_signed.bin
+boot_fit=no
+fdtfile=DEFAULT_FDT_FILE
+bootm_size=0x10000000
+mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
+mmcautodetect=yes
+mmcargs=setenv bootargs console=${console} root=${mmcroot}
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=auth_cntr ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r};
+mmcboot=echo Booting from mmc ...;
+		run mmcargs;
+		if test ${sec_boot} = yes; then
+			if run auth_os; then
+				run boot_os;
+			else
+				echo ERR: failed to authenticate;
+			fi;
+		else
+			if test ${boot_fit} = yes || test ${boot_fit} = try; then
+				bootm ${loadaddr};
+			else
+				if run loadfdt; then
+					run boot_os;
+				else
+					echo WARN: Cannot load the DT;
+				fi;
+			fi;
+		fi;
+netargs=setenv bootargs console=${console} root=/dev/nfs
+		ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=echo Booting from net ...;
+		run netargs;
+		if test ${ip_dyn} = yes; then
+			setenv get_cmd dhcp;
+		else
+			setenv get_cmd tftp;
+		fi;
+		if test ${sec_boot} = yes; then
+			${get_cmd} ${cntr_addr} ${cntr_file};
+			if run auth_os; then
+				run boot_os;
+			else
+				echo ERR: failed to authenticate;
+			fi;
+		else
+			${get_cmd} ${loadaddr} ${image};
+			if test ${boot_fit} = yes || test ${boot_fit} = try; then
+				bootm ${loadaddr};
+			else
+				if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+					run boot_os;
+				else
+					echo WARN: Cannot load the DT;
+				fi;
+			fi;
+		fi;
+bsp_bootcmd=echo Running BSP bootcmd ...;
+			mmc dev ${mmcdev}; if mmc rescan; then
+			if run loadbootscript; then
+				run bootscript;
+			else
+				if test ${sec_boot} = yes; then
+					if run loadcntr; then
+						run mmcboot;
+					else run netboot;
+					fi;
+				else
+					if run loadimage; then
+						run mmcboot;
+					else run netboot;
+					fi;
+				fi;
+			fi;
+		fi;
diff --git a/board/nxp/imx95_frdm/spl.c b/board/nxp/imx95_frdm/spl.c
new file mode 100644
index 00000000000..c8a5b4f9d41
--- /dev/null
+++ b/board/nxp/imx95_frdm/spl.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/sections.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/qb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	puts("Normal Boot\n");
+
+	ret = ele_start_rng();
+	if (ret)
+		printf("Fail to start RNG: %d\n", ret);
+
+	if (IS_ENABLED(CONFIG_SPL_IMX_QB))
+		spl_imx_qb_save();
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_SPL_RECOVER_DATA_SECTION
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		spl_save_restore_data();
+#endif
+
+	timer_init();
+
+	/* Need dm_init() to run before any SCMI calls can be made. */
+	spl_early_init();
+
+	/* Need enable SCMI drivers and ELE driver before enabling console */
+	ret = imx9_probe_mu();
+	if (ret)
+		hang(); /* if MU not probed, nothing can output, just hang here */
+
+	arch_cpu_init();
+
+	preloader_console_init();
+
+	debug("SOC: 0x%x\n", gd->arch.soc_rev);
+	debug("LC: 0x%x\n", gd->arch.lifecycle);
+
+	get_reset_reason(true, false);
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig
index 06449128ba8..609c11580ce 100644
--- a/board/phytec/phycore_imx8mm/Kconfig
+++ b/board/phytec/phycore_imx8mm/Kconfig
@@ -12,5 +12,70 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"
 
+config PHYCORE_IMX8MM_RAM_SIZE_FIX
+	bool "Set phyCORE-i.MX8MM RAM size fix instead of detecting"
+	default false
+	help
+	  RAM size is automatic being detected with the help of
+	  the EEPROM introspection data. Set RAM size to a fix value
+	  instead.
+
+choice
+	prompt "phyCORE-i.MX8MM RAM size"
+	depends on PHYCORE_IMX8MM_RAM_SIZE_FIX
+	default PHYCORE_IMX8MM_RAM_SIZE_2GB
+	help
+	  Select a fixed RAM size instead of EEPROM introspection
+	  data.
+
+config PHYCORE_IMX8MM_RAM_SIZE_1GB
+	bool "1GB RAM"
+	help
+	  Set RAM size fix to 1GB for phyCORE-i.MX8MM
+	  instead of runtime detection from EEPROM.
+
+config PHYCORE_IMX8MM_RAM_SIZE_2GB
+	bool "2GB RAM"
+	help
+	  Set RAM size fix to 2GB for phyCORE-i.MX8MM
+	  instead of runtime detection from EEPROM.
+
+config PHYCORE_IMX8MM_RAM_SIZE_4GB
+	bool "4GB RAM"
+	help
+	  Set RAM size fix to 4GB for phyCORE-i.MX8MM
+	  instead of runtime detection from EEPROM.
+
+endchoice
+
+config PHYCORE_IMX8MM_RAM_STATIC_SOM_REV
+	bool "Set static phyCORE-i.MX8MM SoM revision for RAM timing setup"
+	default false
+	help
+	  phyCORE-i.MX8MM SoM revision 7 uses a updated set of optimized
+	  RAM timings compared to revision 6 and older. Set the SoM
+	  revision during compile time instead of being detected.
+
+choice
+	prompt "phyCORE-i.MX8MM RAM timing SoM revision static config"
+	depends on PHYCORE_IMX8MM_RAM_STATIC_SOM_REV
+	default PHYCORE_IMX8MM_USE_SOM_REV_7
+	help
+	  Use a fixed revision setting instead of runtime
+	  auto detection.
+
+config PHYCORE_IMX8MM_USE_SOM_REV_6
+	bool "RAM Timings for SoM Revisions 6 and older"
+	help
+	  Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revisions 6
+	  and older instead of autodetecting.
+
+config PHYCORE_IMX8MM_USE_SOM_REV_7
+	bool "RAM Timings for SoM Revision 7"
+	help
+	  Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revision 7
+	  instead of autodetecting.
+endchoice
+
 source "board/phytec/common/Kconfig"
 endif
diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.c b/board/phytec/phycore_imx8mm/lpddr4_timing.c
index f5a2f3268b3..162b0209d92 100644
--- a/board/phytec/phycore_imx8mm/lpddr4_timing.c
+++ b/board/phytec/phycore_imx8mm/lpddr4_timing.c
@@ -1,16 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2019 NXP
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Copyright 2025 NXP
+ * Copyright 2025 PHYTEC Messtechnik GmbH
  *
- * Generated code from MX8M_DDR_tool
+ * Code partially generated with DDR Tool v3.6.0_22-aa018543.
+ * DDR PHY FW2017.09
  */
 
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
 
+/* Initialize DDRC registers */
 static struct dram_cfg_param ddr_ddrc_cfg[] = {
-	/** Initialize DDRC registers **/
 	{0x3d400304, 0x1},
 	{0x3d400030, 0x1},
 	{0x3d400000, 0xa1080020},
@@ -20,9 +21,9 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d4000d0, 0xc00305ba},
 	{0x3d4000d4, 0x940000},
 	{0x3d4000dc, 0xd4002d},
-	{0x3d4000e0, 0x310000},
-	{0x3d4000e8, 0x66004d},
-	{0x3d4000ec, 0x16004d},
+	{0x3d4000e0, 0xe10000},
+	{0x3d4000e8, 0x54004d},
+	{0x3d4000ec, 0x15004d},
 	{0x3d400100, 0x191e0c20},
 	{0x3d400104, 0x60630},
 	{0x3d40010c, 0xb0b000},
@@ -37,17 +38,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d400180, 0x2ee0017},
 	{0x3d400184, 0x2605b8e},
 	{0x3d400188, 0x0},
-	{0x3d400190, 0x497820a},
+	{0x3d400190, 0x49b820a},
 	{0x3d400194, 0x80303},
-	{0x3d4001b4, 0x170a},
+	{0x3d4001b4, 0x1b0a},
 	{0x3d4001a0, 0xe0400018},
 	{0x3d4001a4, 0xdf00e4},
 	{0x3d4001a8, 0x80000000},
 	{0x3d4001b0, 0x11},
-	{0x3d4001c0, 0x1},
+	{0x3d4001c0, 0x7},
 	{0x3d4001c4, 0x1},
 	{0x3d4000f4, 0x699},
-	{0x3d400108, 0x70e1617},
+	{0x3d400108, 0x7101817},
 	{0x3d400200, 0x1f},
 	{0x3d40020c, 0x0},
 	{0x3d400210, 0x1f1f},
@@ -66,56 +67,6 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d400498, 0x620096},
 	{0x3d40049c, 0x1100e07},
 	{0x3d4004a0, 0xc8012c},
-	{0x3d402020, 0x20},
-	{0x3d402024, 0x7d00},
-	{0x3d402050, 0x20d040},
-	{0x3d402064, 0x6001c},
-	{0x3d4020dc, 0x840000},
-	{0x3d4020e0, 0x310000},
-	{0x3d4020e8, 0x66004d},
-	{0x3d4020ec, 0x16004d},
-	{0x3d402100, 0xa040105},
-	{0x3d402104, 0x30407},
-	{0x3d402108, 0x203060b},
-	{0x3d40210c, 0x505000},
-	{0x3d402110, 0x2040202},
-	{0x3d402114, 0x2030202},
-	{0x3d402118, 0x1010004},
-	{0x3d40211c, 0x302},
-	{0x3d402130, 0x20300},
-	{0x3d402134, 0xa100002},
-	{0x3d402138, 0x1d},
-	{0x3d402144, 0x14000a},
-	{0x3d402180, 0x640004},
-	{0x3d402190, 0x3818200},
-	{0x3d402194, 0x80303},
-	{0x3d4021b4, 0x100},
-	{0x3d4020f4, 0x599},
-	{0x3d403020, 0x20},
-	{0x3d403024, 0x1f40},
-	{0x3d403050, 0x20d040},
-	{0x3d403064, 0x30007},
-	{0x3d4030dc, 0x840000},
-	{0x3d4030e0, 0x310000},
-	{0x3d4030e8, 0x66004d},
-	{0x3d4030ec, 0x16004d},
-	{0x3d403100, 0xa010102},
-	{0x3d403104, 0x30404},
-	{0x3d403108, 0x203060b},
-	{0x3d40310c, 0x505000},
-	{0x3d403110, 0x2040202},
-	{0x3d403114, 0x2030202},
-	{0x3d403118, 0x1010004},
-	{0x3d40311c, 0x302},
-	{0x3d403130, 0x20300},
-	{0x3d403134, 0xa100002},
-	{0x3d403138, 0x8},
-	{0x3d403144, 0x50003},
-	{0x3d403180, 0x190004},
-	{0x3d403190, 0x3818200},
-	{0x3d403194, 0x80303},
-	{0x3d4031b4, 0x100},
-	{0x3d4030f4, 0x599},
 	{0x3d400028, 0x0},
 };
 
@@ -161,22 +112,6 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x1215f, 0x1ff},
 	{0x1305f, 0x1ff},
 	{0x1315f, 0x1ff},
-	{0x11005f, 0x1ff},
-	{0x11015f, 0x1ff},
-	{0x11105f, 0x1ff},
-	{0x11115f, 0x1ff},
-	{0x11205f, 0x1ff},
-	{0x11215f, 0x1ff},
-	{0x11305f, 0x1ff},
-	{0x11315f, 0x1ff},
-	{0x21005f, 0x1ff},
-	{0x21015f, 0x1ff},
-	{0x21105f, 0x1ff},
-	{0x21115f, 0x1ff},
-	{0x21205f, 0x1ff},
-	{0x21215f, 0x1ff},
-	{0x21305f, 0x1ff},
-	{0x21315f, 0x1ff},
 	{0x55, 0x1ff},
 	{0x1055, 0x1ff},
 	{0x2055, 0x1ff},
@@ -188,87 +123,41 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x8055, 0x1ff},
 	{0x9055, 0x1ff},
 	{0x200c5, 0x19},
-	{0x1200c5, 0x7},
-	{0x2200c5, 0x7},
 	{0x2002e, 0x2},
-	{0x12002e, 0x2},
-	{0x22002e, 0x2},
 	{0x90204, 0x0},
-	{0x190204, 0x0},
-	{0x290204, 0x0},
 	{0x20024, 0x1ab},
 	{0x2003a, 0x0},
-	{0x120024, 0x1ab},
-	{0x2003a, 0x0},
-	{0x220024, 0x1ab},
-	{0x2003a, 0x0},
 	{0x20056, 0x3},
-	{0x120056, 0x3},
-	{0x220056, 0x3},
-	{0x1004d, 0xe00},
-	{0x1014d, 0xe00},
-	{0x1104d, 0xe00},
-	{0x1114d, 0xe00},
-	{0x1204d, 0xe00},
-	{0x1214d, 0xe00},
-	{0x1304d, 0xe00},
-	{0x1314d, 0xe00},
-	{0x11004d, 0xe00},
-	{0x11014d, 0xe00},
-	{0x11104d, 0xe00},
-	{0x11114d, 0xe00},
-	{0x11204d, 0xe00},
-	{0x11214d, 0xe00},
-	{0x11304d, 0xe00},
-	{0x11314d, 0xe00},
-	{0x21004d, 0xe00},
-	{0x21014d, 0xe00},
-	{0x21104d, 0xe00},
-	{0x21114d, 0xe00},
-	{0x21204d, 0xe00},
-	{0x21214d, 0xe00},
-	{0x21304d, 0xe00},
-	{0x21314d, 0xe00},
-	{0x10049, 0xeba},
-	{0x10149, 0xeba},
-	{0x11049, 0xeba},
-	{0x11149, 0xeba},
-	{0x12049, 0xeba},
-	{0x12149, 0xeba},
-	{0x13049, 0xeba},
-	{0x13149, 0xeba},
-	{0x110049, 0xeba},
-	{0x110149, 0xeba},
-	{0x111049, 0xeba},
-	{0x111149, 0xeba},
-	{0x112049, 0xeba},
-	{0x112149, 0xeba},
-	{0x113049, 0xeba},
-	{0x113149, 0xeba},
-	{0x210049, 0xeba},
-	{0x210149, 0xeba},
-	{0x211049, 0xeba},
-	{0x211149, 0xeba},
-	{0x212049, 0xeba},
-	{0x212149, 0xeba},
-	{0x213049, 0xeba},
-	{0x213149, 0xeba},
-	{0x43, 0x63},
-	{0x1043, 0x63},
-	{0x2043, 0x63},
-	{0x3043, 0x63},
-	{0x4043, 0x63},
-	{0x5043, 0x63},
-	{0x6043, 0x63},
-	{0x7043, 0x63},
-	{0x8043, 0x63},
-	{0x9043, 0x63},
+	{0x1004d, 0x680},
+	{0x1014d, 0x680},
+	{0x1104d, 0x680},
+	{0x1114d, 0x680},
+	{0x1204d, 0x680},
+	{0x1214d, 0x680},
+	{0x1304d, 0x680},
+	{0x1314d, 0x680},
+	{0x10049, 0x28a},
+	{0x10149, 0x28a},
+	{0x11049, 0x28a},
+	{0x11149, 0x28a},
+	{0x12049, 0x28a},
+	{0x12149, 0x28a},
+	{0x13049, 0x28a},
+	{0x13149, 0x28a},
+	{0x43, 0x21},
+	{0x1043, 0x21},
+	{0x2043, 0x21},
+	{0x3043, 0x21},
+	{0x4043, 0x21},
+	{0x5043, 0x21},
+	{0x6043, 0x21},
+	{0x7043, 0x21},
+	{0x8043, 0x21},
+	{0x9043, 0x21},
 	{0x20018, 0x3},
 	{0x20075, 0x4},
 	{0x20050, 0x0},
 	{0x20008, 0x2ee},
-	{0x120008, 0x64},
-	{0x220008, 0x19},
 	{0x20088, 0x9},
 	{0x200b2, 0xdc},
 	{0x10043, 0x5a1},
@@ -279,594 +168,741 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x12143, 0x5a1},
 	{0x13043, 0x5a1},
 	{0x13143, 0x5a1},
-	{0x1200b2, 0xdc},
-	{0x110043, 0x5a1},
-	{0x110143, 0x5a1},
-	{0x111043, 0x5a1},
-	{0x111143, 0x5a1},
-	{0x112043, 0x5a1},
-	{0x112143, 0x5a1},
-	{0x113043, 0x5a1},
-	{0x113143, 0x5a1},
-	{0x2200b2, 0xdc},
-	{0x210043, 0x5a1},
-	{0x210143, 0x5a1},
-	{0x211043, 0x5a1},
-	{0x211143, 0x5a1},
-	{0x212043, 0x5a1},
-	{0x212143, 0x5a1},
-	{0x213043, 0x5a1},
-	{0x213143, 0x5a1},
 	{0x200fa, 0x1},
-	{0x1200fa, 0x1},
-	{0x2200fa, 0x1},
 	{0x20019, 0x1},
-	{0x120019, 0x1},
-	{0x220019, 0x1},
-	{0x200f0, 0x660},
+	{0x200f0, 0x0},
 	{0x200f1, 0x0},
 	{0x200f2, 0x4444},
 	{0x200f3, 0x8888},
-	{0x200f4, 0x5665},
+	{0x200f4, 0x5555},
 	{0x200f5, 0x0},
 	{0x200f6, 0x0},
 	{0x200f7, 0xf000},
 	{0x20025, 0x0},
-	{0x2002d, 0x0},
-	{0x12002d, 0x0},
-	{0x22002d, 0x0},
-	{0x200c7, 0x21},
-	{0x1200c7, 0x21},
-	{0x2200c7, 0x21},
+	{0x2002d, 0x1},
 	{0x200ca, 0x24},
 	{0x1200ca, 0x24},
 	{0x2200ca, 0x24},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x21},
+	{0x2200c7, 0x21},
 };
 
-/* ddr phy trained csr */
+/* PHY trained csr */
 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x1005f, 0x0},
+	{0x1015f, 0x0},
+	{0x1105f, 0x0},
+	{0x1115f, 0x0},
+	{0x1205f, 0x0},
+	{0x1215f, 0x0},
+	{0x1305f, 0x0},
+	{0x1315f, 0x0},
+	{0x55, 0x0},
+	{0x1055, 0x0},
+	{0x2055, 0x0},
+	{0x3055, 0x0},
+	{0x4055, 0x0},
+	{0x5055, 0x0},
+	{0x6055, 0x0},
+	{0x7055, 0x0},
+	{0x8055, 0x0},
+	{0x9055, 0x0},
+	{0x200c5, 0x0},
+	{0x2002e, 0x0},
+	{0x90204, 0x0},
+	{0x20024, 0x0},
+	{0x2003a, 0x0},
+	{0x20056, 0x0},
+	{0x1004d, 0x0},
+	{0x1014d, 0x0},
+	{0x1104d, 0x0},
+	{0x1114d, 0x0},
+	{0x1204d, 0x0},
+	{0x1214d, 0x0},
+	{0x1304d, 0x0},
+	{0x1314d, 0x0},
+	{0x10049, 0x0},
+	{0x10149, 0x0},
+	{0x11049, 0x0},
+	{0x11149, 0x0},
+	{0x12049, 0x0},
+	{0x12149, 0x0},
+	{0x13049, 0x0},
+	{0x13149, 0x0},
+	{0x43, 0x0},
+	{0x1043, 0x0},
+	{0x2043, 0x0},
+	{0x3043, 0x0},
+	{0x4043, 0x0},
+	{0x5043, 0x0},
+	{0x6043, 0x0},
+	{0x7043, 0x0},
+	{0x8043, 0x0},
+	{0x9043, 0x0},
+	{0x20018, 0x0},
+	{0x20075, 0x0},
+	{0x20050, 0x0},
+	{0x20008, 0x0},
+	{0x20088, 0x0},
 	{0x200b2, 0x0},
-	{0x1200b2, 0x0},
-	{0x2200b2, 0x0},
-	{0x200cb, 0x0},
 	{0x10043, 0x0},
-	{0x110043, 0x0},
-	{0x210043, 0x0},
 	{0x10143, 0x0},
-	{0x110143, 0x0},
-	{0x210143, 0x0},
 	{0x11043, 0x0},
-	{0x111043, 0x0},
-	{0x211043, 0x0},
 	{0x11143, 0x0},
-	{0x111143, 0x0},
-	{0x211143, 0x0},
 	{0x12043, 0x0},
-	{0x112043, 0x0},
-	{0x212043, 0x0},
 	{0x12143, 0x0},
-	{0x112143, 0x0},
-	{0x212143, 0x0},
 	{0x13043, 0x0},
-	{0x113043, 0x0},
-	{0x213043, 0x0},
 	{0x13143, 0x0},
-	{0x113143, 0x0},
-	{0x213143, 0x0},
-	{0x80, 0x0},
-	{0x100080, 0x0},
-	{0x200080, 0x0},
-	{0x1080, 0x0},
-	{0x101080, 0x0},
-	{0x201080, 0x0},
-	{0x2080, 0x0},
-	{0x102080, 0x0},
-	{0x202080, 0x0},
-	{0x3080, 0x0},
-	{0x103080, 0x0},
-	{0x203080, 0x0},
-	{0x4080, 0x0},
-	{0x104080, 0x0},
-	{0x204080, 0x0},
-	{0x5080, 0x0},
-	{0x105080, 0x0},
-	{0x205080, 0x0},
-	{0x6080, 0x0},
-	{0x106080, 0x0},
-	{0x206080, 0x0},
-	{0x7080, 0x0},
-	{0x107080, 0x0},
-	{0x207080, 0x0},
-	{0x8080, 0x0},
-	{0x108080, 0x0},
-	{0x208080, 0x0},
-	{0x9080, 0x0},
-	{0x109080, 0x0},
-	{0x209080, 0x0},
-	{0x10080, 0x0},
-	{0x110080, 0x0},
-	{0x210080, 0x0},
-	{0x10180, 0x0},
-	{0x110180, 0x0},
-	{0x210180, 0x0},
-	{0x11080, 0x0},
-	{0x111080, 0x0},
-	{0x211080, 0x0},
-	{0x11180, 0x0},
-	{0x111180, 0x0},
-	{0x211180, 0x0},
-	{0x12080, 0x0},
-	{0x112080, 0x0},
-	{0x212080, 0x0},
-	{0x12180, 0x0},
-	{0x112180, 0x0},
-	{0x212180, 0x0},
-	{0x13080, 0x0},
-	{0x113080, 0x0},
-	{0x213080, 0x0},
-	{0x13180, 0x0},
-	{0x113180, 0x0},
-	{0x213180, 0x0},
-	{0x10081, 0x0},
-	{0x110081, 0x0},
-	{0x210081, 0x0},
-	{0x10181, 0x0},
-	{0x110181, 0x0},
-	{0x210181, 0x0},
-	{0x11081, 0x0},
-	{0x111081, 0x0},
-	{0x211081, 0x0},
-	{0x11181, 0x0},
-	{0x111181, 0x0},
-	{0x211181, 0x0},
-	{0x12081, 0x0},
-	{0x112081, 0x0},
-	{0x212081, 0x0},
-	{0x12181, 0x0},
-	{0x112181, 0x0},
-	{0x212181, 0x0},
-	{0x13081, 0x0},
-	{0x113081, 0x0},
-	{0x213081, 0x0},
-	{0x13181, 0x0},
-	{0x113181, 0x0},
-	{0x213181, 0x0},
-	{0x100d0, 0x0},
-	{0x1100d0, 0x0},
-	{0x2100d0, 0x0},
-	{0x101d0, 0x0},
-	{0x1101d0, 0x0},
-	{0x2101d0, 0x0},
-	{0x110d0, 0x0},
-	{0x1110d0, 0x0},
-	{0x2110d0, 0x0},
-	{0x111d0, 0x0},
-	{0x1111d0, 0x0},
-	{0x2111d0, 0x0},
-	{0x120d0, 0x0},
-	{0x1120d0, 0x0},
-	{0x2120d0, 0x0},
-	{0x121d0, 0x0},
-	{0x1121d0, 0x0},
-	{0x2121d0, 0x0},
-	{0x130d0, 0x0},
-	{0x1130d0, 0x0},
-	{0x2130d0, 0x0},
-	{0x131d0, 0x0},
-	{0x1131d0, 0x0},
-	{0x2131d0, 0x0},
-	{0x100d1, 0x0},
-	{0x1100d1, 0x0},
-	{0x2100d1, 0x0},
-	{0x101d1, 0x0},
-	{0x1101d1, 0x0},
-	{0x2101d1, 0x0},
-	{0x110d1, 0x0},
-	{0x1110d1, 0x0},
-	{0x2110d1, 0x0},
-	{0x111d1, 0x0},
-	{0x1111d1, 0x0},
-	{0x2111d1, 0x0},
-	{0x120d1, 0x0},
-	{0x1120d1, 0x0},
-	{0x2120d1, 0x0},
-	{0x121d1, 0x0},
-	{0x1121d1, 0x0},
-	{0x2121d1, 0x0},
-	{0x130d1, 0x0},
-	{0x1130d1, 0x0},
-	{0x2130d1, 0x0},
-	{0x131d1, 0x0},
-	{0x1131d1, 0x0},
-	{0x2131d1, 0x0},
-	{0x10068, 0x0},
-	{0x10168, 0x0},
-	{0x10268, 0x0},
-	{0x10368, 0x0},
-	{0x10468, 0x0},
-	{0x10568, 0x0},
-	{0x10668, 0x0},
-	{0x10768, 0x0},
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+	{0x4006d, 0x0},
+	{0x4000e, 0x0},
+	{0x4002e, 0x0},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x0},
+	{0x4002f, 0x0},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x0},
+	{0x40030, 0x0},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x0},
+	{0x40031, 0x0},
+	{0x40051, 0x0},
+	{0x40071, 0x0},
+	{0x40012, 0x0},
+	{0x40032, 0x0},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x0},
+	{0x40033, 0x0},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x0},
+	{0x40034, 0x0},
+	{0x40054, 0x0},
+	{0x40074, 0x0},
+	{0x40015, 0x0},
+	{0x40035, 0x0},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x0},
+	{0x40036, 0x0},
+	{0x40056, 0x0},
+	{0x40076, 0x0},
+	{0x40017, 0x0},
+	{0x40037, 0x0},
+	{0x40057, 0x0},
+	{0x40077, 0x0},
+	{0x40018, 0x0},
+	{0x40038, 0x0},
+	{0x40058, 0x0},
+	{0x40078, 0x0},
+	{0x40019, 0x0},
+	{0x40039, 0x0},
+	{0x40059, 0x0},
+	{0x40079, 0x0},
+	{0x4001a, 0x0},
+	{0x4003a, 0x0},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x0},
+	{0x900a9, 0x0},
+	{0x900aa, 0x0},
+	{0x900ab, 0x0},
+	{0x900ac, 0x0},
+	{0x900ad, 0x0},
+	{0x900ae, 0x0},
+	{0x900af, 0x0},
+	{0x900b0, 0x0},
+	{0x900b1, 0x0},
+	{0x900b2, 0x0},
+	{0x900b3, 0x0},
+	{0x900b4, 0x0},
+	{0x900b5, 0x0},
+	{0x900b6, 0x0},
+	{0x900b7, 0x0},
+	{0x900b8, 0x0},
+	{0x900b9, 0x0},
+	{0x900ba, 0x0},
+	{0x900bb, 0x0},
+	{0x900bc, 0x0},
+	{0x900bd, 0x0},
+	{0x900be, 0x0},
+	{0x900bf, 0x0},
+	{0x900c0, 0x0},
+	{0x900c1, 0x0},
+	{0x900c2, 0x0},
+	{0x900c3, 0x0},
+	{0x900c4, 0x0},
+	{0x900c5, 0x0},
+	{0x900c6, 0x0},
+	{0x900c7, 0x0},
+	{0x900c8, 0x0},
+	{0x900c9, 0x0},
+	{0x900ca, 0x0},
+	{0x900cb, 0x0},
+	{0x900cc, 0x0},
+	{0x900cd, 0x0},
+	{0x900ce, 0x0},
+	{0x900cf, 0x0},
+	{0x900d0, 0x0},
+	{0x900d1, 0x0},
+	{0x900d2, 0x0},
+	{0x900d3, 0x0},
+	{0x900d4, 0x0},
+	{0x900d5, 0x0},
+	{0x900d6, 0x0},
+	{0x900d7, 0x0},
+	{0x900d8, 0x0},
+	{0x900d9, 0x0},
+	{0x900da, 0x0},
+	{0x900db, 0x0},
+	{0x900dc, 0x0},
+	{0x900dd, 0x0},
+	{0x900de, 0x0},
+	{0x900df, 0x0},
+	{0x900e0, 0x0},
+	{0x900e1, 0x0},
+	{0x900e2, 0x0},
+	{0x900e3, 0x0},
+	{0x900e4, 0x0},
+	{0x900e5, 0x0},
+	{0x900e6, 0x0},
+	{0x900e7, 0x0},
+	{0x900e8, 0x0},
+	{0x900e9, 0x0},
+	{0x900ea, 0x0},
+	{0x900eb, 0x0},
+	{0x900ec, 0x0},
+	{0x900ed, 0x0},
+	{0x900ee, 0x0},
+	{0x900ef, 0x0},
+	{0x900f0, 0x0},
+	{0x900f1, 0x0},
+	{0x900f2, 0x0},
+	{0x900f3, 0x0},
+	{0x900f4, 0x0},
+	{0x900f5, 0x0},
+	{0x900f6, 0x0},
+	{0x900f7, 0x0},
+	{0x900f8, 0x0},
+	{0x900f9, 0x0},
+	{0x900fa, 0x0},
+	{0x900fb, 0x0},
+	{0x900fc, 0x0},
+	{0x900fd, 0x0},
+	{0x900fe, 0x0},
+	{0x900ff, 0x0},
+	{0x90100, 0x0},
+	{0x90101, 0x0},
+	{0x90102, 0x0},
+	{0x90103, 0x0},
+	{0x90104, 0x0},
+	{0x90105, 0x0},
+	{0x90106, 0x0},
+	{0x90107, 0x0},
+	{0x90108, 0x0},
+	{0x90109, 0x0},
+	{0x9010a, 0x0},
+	{0x9010b, 0x0},
+	{0x9010c, 0x0},
+	{0x9010d, 0x0},
+	{0x9010e, 0x0},
+	{0x9010f, 0x0},
+	{0x90110, 0x0},
+	{0x90111, 0x0},
+	{0x90112, 0x0},
+	{0x90113, 0x0},
+	{0x90114, 0x0},
+	{0x90115, 0x0},
+	{0x90116, 0x0},
+	{0x90117, 0x0},
+	{0x90118, 0x0},
+	{0x90119, 0x0},
+	{0x9011a, 0x0},
+	{0x9011b, 0x0},
+	{0x9011c, 0x0},
+	{0x9011d, 0x0},
+	{0x9011e, 0x0},
+	{0x9011f, 0x0},
+	{0x90120, 0x0},
+	{0x90121, 0x0},
+	{0x90122, 0x0},
+	{0x90123, 0x0},
+	{0x90124, 0x0},
+	{0x90125, 0x0},
+	{0x90126, 0x0},
+	{0x90127, 0x0},
+	{0x90128, 0x0},
+	{0x90129, 0x0},
+	{0x9012a, 0x0},
+	{0x9012b, 0x0},
+	{0x9012c, 0x0},
+	{0x9012d, 0x0},
+	{0x9012e, 0x0},
+	{0x9012f, 0x0},
+	{0x90130, 0x0},
+	{0x90131, 0x0},
+	{0x90132, 0x0},
+	{0x90133, 0x0},
+	{0x90134, 0x0},
+	{0x90135, 0x0},
+	{0x90136, 0x0},
+	{0x90137, 0x0},
+	{0x90138, 0x0},
+	{0x90139, 0x0},
+	{0x9013a, 0x0},
+	{0x9013b, 0x0},
+	{0x9013c, 0x0},
+	{0x9013d, 0x0},
+	{0x9013e, 0x0},
+	{0x9013f, 0x0},
+	{0x90140, 0x0},
+	{0x90141, 0x0},
+	{0x90142, 0x0},
+	{0x90143, 0x0},
+	{0x90144, 0x0},
+	{0x90145, 0x0},
+	{0x90146, 0x0},
+	{0x90147, 0x0},
+	{0x90148, 0x0},
+	{0x90149, 0x0},
+	{0x9014a, 0x0},
+	{0x9014b, 0x0},
+	{0x9014c, 0x0},
+	{0x9014d, 0x0},
+	{0x9014e, 0x0},
+	{0x9014f, 0x0},
+	{0x90150, 0x0},
+	{0x90151, 0x0},
+	{0x90152, 0x0},
+	{0x90153, 0x0},
+	{0x90154, 0x0},
+	{0x90155, 0x0},
+	{0x90156, 0x0},
+	{0x90157, 0x0},
+	{0x90158, 0x0},
+	{0x90159, 0x0},
+	{0x9015a, 0x0},
+	{0x9015b, 0x0},
+	{0x9015c, 0x0},
+	{0x9015d, 0x0},
+	{0x9015e, 0x0},
+	{0x9015f, 0x0},
+	{0x90160, 0x0},
+	{0x90161, 0x0},
+	{0x90162, 0x0},
+	{0x90163, 0x0},
+	{0x90164, 0x0},
+	{0x90165, 0x0},
+	{0x90166, 0x0},
+	{0x90167, 0x0},
+	{0x90168, 0x0},
+	{0x90169, 0x0},
+	{0x9016a, 0x0},
+	{0x9016b, 0x0},
+	{0x9016c, 0x0},
+	{0x9016d, 0x0},
+	{0x9016e, 0x0},
+	{0x9016f, 0x0},
+	{0x90170, 0x0},
+	{0x90171, 0x0},
+	{0x90172, 0x0},
+	{0x90173, 0x0},
+	{0x90174, 0x0},
+	{0x90175, 0x0},
+	{0x90176, 0x0},
+	{0x90177, 0x0},
+	{0x90178, 0x0},
+	{0x90179, 0x0},
+	{0x9017a, 0x0},
+	{0x9017b, 0x0},
+	{0x9017c, 0x0},
+	{0x9017d, 0x0},
+	{0x9017e, 0x0},
+	{0x9017f, 0x0},
+	{0x90180, 0x0},
+	{0x90181, 0x0},
+	{0x90182, 0x0},
+	{0x90183, 0x0},
+	{0x90184, 0x0},
+	{0x90185, 0x0},
+	{0x90186, 0x0},
+	{0x90187, 0x0},
+	{0x90188, 0x0},
+	{0x90189, 0x0},
+	{0x9018a, 0x0},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x0},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x0},
+	{0x90017, 0x0},
+	{0x9001f, 0x0},
+	{0x90026, 0x0},
+	{0x400d0, 0x0},
+	{0x400d1, 0x0},
+	{0x400d2, 0x0},
+	{0x400d3, 0x0},
+	{0x400d4, 0x0},
+	{0x400d5, 0x0},
+	{0x400d6, 0x0},
+	{0x400d7, 0x0},
+	{0x2000b, 0x0},
+	{0x2000c, 0x0},
+	{0x2000d, 0x0},
+	{0x2000e, 0x0},
+	{0x9000c, 0x0},
+	{0x9000d, 0x0},
+	{0x9000e, 0x0},
+	{0x9000f, 0x0},
+	{0x90010, 0x0},
+	{0x90011, 0x0},
+	{0x90012, 0x0},
+	{0x90013, 0x0},
 	{0x20010, 0x0},
-	{0x120010, 0x0},
-	{0x220010, 0x0},
 	{0x20011, 0x0},
-	{0x120011, 0x0},
-	{0x220011, 0x0},
+	{0x40080, 0x0},
+	{0x40081, 0x0},
+	{0x40082, 0x0},
+	{0x40083, 0x0},
+	{0x40084, 0x0},
+	{0x40085, 0x0},
+	{0x400fd, 0x0},
+	{0x10011, 0x0},
+	{0x10012, 0x0},
+	{0x10013, 0x0},
+	{0x10018, 0x0},
+	{0x10002, 0x0},
+	{0x100b2, 0x0},
+	{0x101b4, 0x0},
+	{0x102b4, 0x0},
+	{0x103b4, 0x0},
+	{0x104b4, 0x0},
+	{0x105b4, 0x0},
+	{0x106b4, 0x0},
+	{0x107b4, 0x0},
+	{0x108b4, 0x0},
+	{0x11011, 0x0},
+	{0x11012, 0x0},
+	{0x11013, 0x0},
+	{0x11018, 0x0},
+	{0x11002, 0x0},
+	{0x110b2, 0x0},
+	{0x111b4, 0x0},
+	{0x112b4, 0x0},
+	{0x113b4, 0x0},
+	{0x114b4, 0x0},
+	{0x115b4, 0x0},
+	{0x116b4, 0x0},
+	{0x117b4, 0x0},
+	{0x118b4, 0x0},
+	{0x12011, 0x0},
+	{0x12012, 0x0},
+	{0x12013, 0x0},
+	{0x12018, 0x0},
+	{0x12002, 0x0},
+	{0x120b2, 0x0},
+	{0x121b4, 0x0},
+	{0x122b4, 0x0},
+	{0x123b4, 0x0},
+	{0x124b4, 0x0},
+	{0x125b4, 0x0},
+	{0x126b4, 0x0},
+	{0x127b4, 0x0},
+	{0x128b4, 0x0},
+	{0x13011, 0x0},
+	{0x13012, 0x0},
+	{0x13013, 0x0},
+	{0x13018, 0x0},
+	{0x13002, 0x0},
+	{0x130b2, 0x0},
+	{0x131b4, 0x0},
+	{0x132b4, 0x0},
+	{0x133b4, 0x0},
+	{0x134b4, 0x0},
+	{0x135b4, 0x0},
+	{0x136b4, 0x0},
+	{0x137b4, 0x0},
+	{0x138b4, 0x0},
+	{0xc0080, 0x0},
+	{0x200cb, 0x0},
+	{0x10068, 0x0},
+	{0x10069, 0x0},
+	{0x10168, 0x0},
+	{0x10169, 0x0},
+	{0x100aa, 0x0},
+	{0x10062, 0x0},
+	{0x10001, 0x0},
+	{0x11068, 0x0},
+	{0x11069, 0x0},
+	{0x11168, 0x0},
+	{0x11169, 0x0},
+	{0x110aa, 0x0},
+	{0x11062, 0x0},
+	{0x11001, 0x0},
+	{0x12068, 0x0},
+	{0x12069, 0x0},
+	{0x12168, 0x0},
+	{0x12169, 0x0},
+	{0x120aa, 0x0},
+	{0x12062, 0x0},
+	{0x12001, 0x0},
+	{0x13068, 0x0},
+	{0x13069, 0x0},
+	{0x13168, 0x0},
+	{0x13169, 0x0},
+	{0x130aa, 0x0},
+	{0x13062, 0x0},
+	{0x13001, 0x0},
+	{0x80, 0x0},
+	{0x1080, 0x0},
+	{0x2080, 0x0},
+	{0x3080, 0x0},
+	{0x4080, 0x0},
+	{0x5080, 0x0},
+	{0x6080, 0x0},
+	{0x7080, 0x0},
+	{0x8080, 0x0},
+	{0x9080, 0x0},
+	{0x10020, 0x0},
+	{0x10080, 0x0},
+	{0x10081, 0x0},
+	{0x100d0, 0x0},
+	{0x100d1, 0x0},
+	{0x1008c, 0x0},
+	{0x1008d, 0x0},
+	{0x10180, 0x0},
+	{0x10181, 0x0},
+	{0x101d0, 0x0},
+	{0x101d1, 0x0},
+	{0x1018c, 0x0},
+	{0x1018d, 0x0},
+	{0x100c0, 0x0},
+	{0x100c1, 0x0},
+	{0x101c0, 0x0},
+	{0x101c1, 0x0},
+	{0x102c0, 0x0},
+	{0x102c1, 0x0},
+	{0x103c0, 0x0},
+	{0x103c1, 0x0},
+	{0x104c0, 0x0},
+	{0x104c1, 0x0},
+	{0x105c0, 0x0},
+	{0x105c1, 0x0},
+	{0x106c0, 0x0},
+	{0x106c1, 0x0},
+	{0x107c0, 0x0},
+	{0x107c1, 0x0},
+	{0x108c0, 0x0},
+	{0x108c1, 0x0},
 	{0x100ae, 0x0},
-	{0x1100ae, 0x0},
-	{0x2100ae, 0x0},
 	{0x100af, 0x0},
-	{0x1100af, 0x0},
-	{0x2100af, 0x0},
-	{0x110ae, 0x0},
-	{0x1110ae, 0x0},
-	{0x2110ae, 0x0},
-	{0x110af, 0x0},
-	{0x1110af, 0x0},
-	{0x2110af, 0x0},
-	{0x120ae, 0x0},
-	{0x1120ae, 0x0},
-	{0x2120ae, 0x0},
-	{0x120af, 0x0},
-	{0x1120af, 0x0},
-	{0x2120af, 0x0},
-	{0x130ae, 0x0},
-	{0x1130ae, 0x0},
-	{0x2130ae, 0x0},
-	{0x130af, 0x0},
-	{0x1130af, 0x0},
-	{0x2130af, 0x0},
-	{0x20020, 0x0},
-	{0x120020, 0x0},
-	{0x220020, 0x0},
 	{0x100a0, 0x0},
 	{0x100a1, 0x0},
 	{0x100a2, 0x0},
@@ -875,6 +911,39 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x100a5, 0x0},
 	{0x100a6, 0x0},
 	{0x100a7, 0x0},
+	{0x11020, 0x0},
+	{0x11080, 0x0},
+	{0x11081, 0x0},
+	{0x110d0, 0x0},
+	{0x110d1, 0x0},
+	{0x1108c, 0x0},
+	{0x1108d, 0x0},
+	{0x11180, 0x0},
+	{0x11181, 0x0},
+	{0x111d0, 0x0},
+	{0x111d1, 0x0},
+	{0x1118c, 0x0},
+	{0x1118d, 0x0},
+	{0x110c0, 0x0},
+	{0x110c1, 0x0},
+	{0x111c0, 0x0},
+	{0x111c1, 0x0},
+	{0x112c0, 0x0},
+	{0x112c1, 0x0},
+	{0x113c0, 0x0},
+	{0x113c1, 0x0},
+	{0x114c0, 0x0},
+	{0x114c1, 0x0},
+	{0x115c0, 0x0},
+	{0x115c1, 0x0},
+	{0x116c0, 0x0},
+	{0x116c1, 0x0},
+	{0x117c0, 0x0},
+	{0x117c1, 0x0},
+	{0x118c0, 0x0},
+	{0x118c1, 0x0},
+	{0x110ae, 0x0},
+	{0x110af, 0x0},
 	{0x110a0, 0x0},
 	{0x110a1, 0x0},
 	{0x110a2, 0x0},
@@ -883,6 +952,39 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x110a5, 0x0},
 	{0x110a6, 0x0},
 	{0x110a7, 0x0},
+	{0x12020, 0x0},
+	{0x12080, 0x0},
+	{0x12081, 0x0},
+	{0x120d0, 0x0},
+	{0x120d1, 0x0},
+	{0x1208c, 0x0},
+	{0x1208d, 0x0},
+	{0x12180, 0x0},
+	{0x12181, 0x0},
+	{0x121d0, 0x0},
+	{0x121d1, 0x0},
+	{0x1218c, 0x0},
+	{0x1218d, 0x0},
+	{0x120c0, 0x0},
+	{0x120c1, 0x0},
+	{0x121c0, 0x0},
+	{0x121c1, 0x0},
+	{0x122c0, 0x0},
+	{0x122c1, 0x0},
+	{0x123c0, 0x0},
+	{0x123c1, 0x0},
+	{0x124c0, 0x0},
+	{0x124c1, 0x0},
+	{0x125c0, 0x0},
+	{0x125c1, 0x0},
+	{0x126c0, 0x0},
+	{0x126c1, 0x0},
+	{0x127c0, 0x0},
+	{0x127c1, 0x0},
+	{0x128c0, 0x0},
+	{0x128c1, 0x0},
+	{0x120ae, 0x0},
+	{0x120af, 0x0},
 	{0x120a0, 0x0},
 	{0x120a1, 0x0},
 	{0x120a2, 0x0},
@@ -891,6 +993,39 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x120a5, 0x0},
 	{0x120a6, 0x0},
 	{0x120a7, 0x0},
+	{0x13020, 0x0},
+	{0x13080, 0x0},
+	{0x13081, 0x0},
+	{0x130d0, 0x0},
+	{0x130d1, 0x0},
+	{0x1308c, 0x0},
+	{0x1308d, 0x0},
+	{0x13180, 0x0},
+	{0x13181, 0x0},
+	{0x131d0, 0x0},
+	{0x131d1, 0x0},
+	{0x1318c, 0x0},
+	{0x1318d, 0x0},
+	{0x130c0, 0x0},
+	{0x130c1, 0x0},
+	{0x131c0, 0x0},
+	{0x131c1, 0x0},
+	{0x132c0, 0x0},
+	{0x132c1, 0x0},
+	{0x133c0, 0x0},
+	{0x133c1, 0x0},
+	{0x134c0, 0x0},
+	{0x134c1, 0x0},
+	{0x135c0, 0x0},
+	{0x135c1, 0x0},
+	{0x136c0, 0x0},
+	{0x136c1, 0x0},
+	{0x137c0, 0x0},
+	{0x137c1, 0x0},
+	{0x138c0, 0x0},
+	{0x138c1, 0x0},
+	{0x130ae, 0x0},
+	{0x130af, 0x0},
 	{0x130a0, 0x0},
 	{0x130a1, 0x0},
 	{0x130a2, 0x0},
@@ -899,306 +1034,108 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x130a5, 0x0},
 	{0x130a6, 0x0},
 	{0x130a7, 0x0},
-	{0x2007c, 0x0},
-	{0x12007c, 0x0},
-	{0x22007c, 0x0},
-	{0x2007d, 0x0},
-	{0x12007d, 0x0},
-	{0x22007d, 0x0},
-	{0x400fd, 0x0},
-	{0x400c0, 0x0},
 	{0x90201, 0x0},
-	{0x190201, 0x0},
-	{0x290201, 0x0},
 	{0x90202, 0x0},
-	{0x190202, 0x0},
-	{0x290202, 0x0},
 	{0x90203, 0x0},
-	{0x190203, 0x0},
-	{0x290203, 0x0},
-	{0x90204, 0x0},
-	{0x190204, 0x0},
-	{0x290204, 0x0},
 	{0x90205, 0x0},
-	{0x190205, 0x0},
-	{0x290205, 0x0},
 	{0x90206, 0x0},
-	{0x190206, 0x0},
-	{0x290206, 0x0},
 	{0x90207, 0x0},
-	{0x190207, 0x0},
-	{0x290207, 0x0},
 	{0x90208, 0x0},
-	{0x190208, 0x0},
-	{0x290208, 0x0},
-	{0x10062, 0x0},
-	{0x10162, 0x0},
-	{0x10262, 0x0},
-	{0x10362, 0x0},
-	{0x10462, 0x0},
-	{0x10562, 0x0},
-	{0x10662, 0x0},
-	{0x10762, 0x0},
-	{0x10862, 0x0},
-	{0x11062, 0x0},
-	{0x11162, 0x0},
-	{0x11262, 0x0},
-	{0x11362, 0x0},
-	{0x11462, 0x0},
-	{0x11562, 0x0},
-	{0x11662, 0x0},
-	{0x11762, 0x0},
-	{0x11862, 0x0},
-	{0x12062, 0x0},
-	{0x12162, 0x0},
-	{0x12262, 0x0},
-	{0x12362, 0x0},
-	{0x12462, 0x0},
-	{0x12562, 0x0},
-	{0x12662, 0x0},
-	{0x12762, 0x0},
-	{0x12862, 0x0},
-	{0x13062, 0x0},
-	{0x13162, 0x0},
-	{0x13262, 0x0},
-	{0x13362, 0x0},
-	{0x13462, 0x0},
-	{0x13562, 0x0},
-	{0x13662, 0x0},
-	{0x13762, 0x0},
-	{0x13862, 0x0},
+	{0x2007c, 0x0},
+	{0x2007d, 0x0},
+	{0x20020, 0x0},
+	{0x20072, 0x0},
+	{0x20073, 0x0},
 	{0x20077, 0x0},
-	{0x10001, 0x0},
-	{0x11001, 0x0},
-	{0x12001, 0x0},
-	{0x13001, 0x0},
+	{0x400c0, 0x0},
 	{0x10040, 0x0},
 	{0x10140, 0x0},
-	{0x10240, 0x0},
-	{0x10340, 0x0},
-	{0x10440, 0x0},
-	{0x10540, 0x0},
-	{0x10640, 0x0},
-	{0x10740, 0x0},
-	{0x10840, 0x0},
-	{0x10030, 0x0},
-	{0x10130, 0x0},
-	{0x10230, 0x0},
-	{0x10330, 0x0},
-	{0x10430, 0x0},
-	{0x10530, 0x0},
-	{0x10630, 0x0},
-	{0x10730, 0x0},
-	{0x10830, 0x0},
 	{0x11040, 0x0},
 	{0x11140, 0x0},
-	{0x11240, 0x0},
-	{0x11340, 0x0},
-	{0x11440, 0x0},
-	{0x11540, 0x0},
-	{0x11640, 0x0},
-	{0x11740, 0x0},
-	{0x11840, 0x0},
-	{0x11030, 0x0},
-	{0x11130, 0x0},
-	{0x11230, 0x0},
-	{0x11330, 0x0},
-	{0x11430, 0x0},
-	{0x11530, 0x0},
-	{0x11630, 0x0},
-	{0x11730, 0x0},
-	{0x11830, 0x0},
 	{0x12040, 0x0},
 	{0x12140, 0x0},
-	{0x12240, 0x0},
-	{0x12340, 0x0},
-	{0x12440, 0x0},
-	{0x12540, 0x0},
-	{0x12640, 0x0},
-	{0x12740, 0x0},
-	{0x12840, 0x0},
-	{0x12030, 0x0},
-	{0x12130, 0x0},
-	{0x12230, 0x0},
-	{0x12330, 0x0},
-	{0x12430, 0x0},
-	{0x12530, 0x0},
-	{0x12630, 0x0},
-	{0x12730, 0x0},
-	{0x12830, 0x0},
 	{0x13040, 0x0},
 	{0x13140, 0x0},
-	{0x13240, 0x0},
-	{0x13340, 0x0},
-	{0x13440, 0x0},
-	{0x13540, 0x0},
-	{0x13640, 0x0},
-	{0x13740, 0x0},
-	{0x13840, 0x0},
-	{0x13030, 0x0},
-	{0x13130, 0x0},
-	{0x13230, 0x0},
-	{0x13330, 0x0},
-	{0x13430, 0x0},
-	{0x13530, 0x0},
-	{0x13630, 0x0},
-	{0x13730, 0x0},
-	{0x13830, 0x0},
 };
-/* P0 message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp0_cfg[] = {
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{0xd0000, 0x0},
 	{0x54003, 0xbb8},
 	{0x54004, 0x2},
-	{0x54005, 0x2228},
+	{0x54005, 0x5030},
 	{0x54006, 0x11},
 	{0x54008, 0x131f},
 	{0x54009, 0xc8},
 	{0x5400b, 0x2},
 	{0x54012, 0x110},
 	{0x54019, 0x2dd4},
-	{0x5401a, 0x31},
-	{0x5401b, 0x4d66},
+	{0x5401a, 0xe1},
+	{0x5401b, 0x4d54},
 	{0x5401c, 0x4d00},
-	{0x5401e, 0x16},
+	{0x5401e, 0x15},
 	{0x5401f, 0x2dd4},
-	{0x54020, 0x31},
-	{0x54021, 0x4d66},
+	{0x54020, 0xe1},
+	{0x54021, 0x4d54},
 	{0x54022, 0x4d00},
-	{0x54024, 0x16},
+	{0x54024, 0x15},
 	{0x5402b, 0x1000},
 	{0x5402c, 0x1},
 	{0x54032, 0xd400},
-	{0x54033, 0x312d},
-	{0x54034, 0x6600},
+	{0x54033, 0xe12d},
+	{0x54034, 0x5400},
 	{0x54035, 0x4d},
 	{0x54036, 0x4d},
-	{0x54037, 0x1600},
+	{0x54037, 0x1500},
 	{0x54038, 0xd400},
-	{0x54039, 0x312d},
-	{0x5403a, 0x6600},
+	{0x54039, 0xe12d},
+	{0x5403a, 0x5400},
 	{0x5403b, 0x4d},
 	{0x5403c, 0x4d},
-	{0x5403d, 0x1600},
-	{0xd0000, 0x1},
+	{0x5403d, 0x1500},
+	{0xd0000, 0x1}
 };
 
-/* P1 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp1_cfg[] = {
-	{0xd0000, 0x0},
-	{0x54002, 0x101},
-	{0x54003, 0x190},
-	{0x54004, 0x2},
-	{0x54005, 0x2228},
-	{0x54006, 0x11},
-	{0x54008, 0x121f},
-	{0x54009, 0xc8},
-	{0x5400b, 0x2},
-	{0x54012, 0x110},
-	{0x54019, 0x84},
-	{0x5401a, 0x31},
-	{0x5401b, 0x4d66},
-	{0x5401c, 0x4d00},
-	{0x5401e, 0x16},
-	{0x5401f, 0x84},
-	{0x54020, 0x31},
-	{0x54021, 0x4d66},
-	{0x54022, 0x4d00},
-	{0x54024, 0x16},
-	{0x5402b, 0x1000},
-	{0x5402c, 0x1},
-	{0x54032, 0x8400},
-	{0x54033, 0x3100},
-	{0x54034, 0x6600},
-	{0x54035, 0x4d},
-	{0x54036, 0x4d},
-	{0x54037, 0x1600},
-	{0x54038, 0x8400},
-	{0x54039, 0x3100},
-	{0x5403a, 0x6600},
-	{0x5403b, 0x4d},
-	{0x5403c, 0x4d},
-	{0x5403d, 0x1600},
-	{0xd0000, 0x1},
-};
 
-/* P2 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp2_cfg[] = {
-	{0xd0000, 0x0},
-	{0x54002, 0x102},
-	{0x54003, 0x64},
-	{0x54004, 0x2},
-	{0x54005, 0x2228},
-	{0x54006, 0x11},
-	{0x54008, 0x121f},
-	{0x54009, 0xc8},
-	{0x5400b, 0x2},
-	{0x54012, 0x110},
-	{0x54019, 0x84},
-	{0x5401a, 0x31},
-	{0x5401b, 0x4d66},
-	{0x5401c, 0x4d00},
-	{0x5401e, 0x16},
-	{0x5401f, 0x84},
-	{0x54020, 0x31},
-	{0x54021, 0x4d66},
-	{0x54022, 0x4d00},
-	{0x54024, 0x16},
-	{0x5402b, 0x1000},
-	{0x5402c, 0x1},
-	{0x54032, 0x8400},
-	{0x54033, 0x3100},
-	{0x54034, 0x6600},
-	{0x54035, 0x4d},
-	{0x54036, 0x4d},
-	{0x54037, 0x1600},
-	{0x54038, 0x8400},
-	{0x54039, 0x3100},
-	{0x5403a, 0x6600},
-	{0x5403b, 0x4d},
-	{0x5403c, 0x4d},
-	{0x5403d, 0x1600},
-	{0xd0000, 0x1},
-};
-
-/* P0 2D message block paremeter for training firmware */
+/* P0 2D message block parameter for training firmware */
 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{0xd0000, 0x0},
 	{0x54003, 0xbb8},
 	{0x54004, 0x2},
-	{0x54005, 0x2228},
+	{0x54005, 0x5030},
 	{0x54006, 0x11},
 	{0x54008, 0x61},
 	{0x54009, 0xc8},
 	{0x5400b, 0x2},
+	{0x5400d, 0x100},
 	{0x5400f, 0x100},
 	{0x54010, 0x1f7f},
 	{0x54012, 0x110},
 	{0x54019, 0x2dd4},
-	{0x5401a, 0x31},
-	{0x5401b, 0x4d66},
+	{0x5401a, 0xe1},
+	{0x5401b, 0x4d54},
 	{0x5401c, 0x4d00},
-	{0x5401e, 0x16},
+	{0x5401e, 0x15},
 	{0x5401f, 0x2dd4},
-	{0x54020, 0x31},
-	{0x54021, 0x4d66},
+	{0x54020, 0xe1},
+	{0x54021, 0x4d54},
 	{0x54022, 0x4d00},
-	{0x54024, 0x16},
+	{0x54024, 0x15},
 	{0x5402b, 0x1000},
 	{0x5402c, 0x1},
 	{0x54032, 0xd400},
-	{0x54033, 0x312d},
-	{0x54034, 0x6600},
+	{0x54033, 0xe12d},
+	{0x54034, 0x5400},
 	{0x54035, 0x4d},
 	{0x54036, 0x4d},
-	{0x54037, 0x1600},
+	{0x54037, 0x1500},
 	{0x54038, 0xd400},
-	{0x54039, 0x312d},
-	{0x5403a, 0x6600},
+	{0x54039, 0xe12d},
+	{0x5403a, 0x5400},
 	{0x5403b, 0x4d},
 	{0x5403c, 0x4d},
-	{0x5403d, 0x1600},
-	{0xd0000, 0x1},
+	{0x5403d, 0x1500},
+	{0xd0000, 0x1}
 };
 
 /* DRAM PHY init engine image */
@@ -1691,18 +1628,10 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{0x400d6, 0x20a},
 	{0x400d7, 0x20b},
 	{0x2003a, 0x2},
-	{0x2000b, 0x34b},
+	{0x2000b, 0x5d},
 	{0x2000c, 0xbb},
 	{0x2000d, 0x753},
 	{0x2000e, 0x2c},
-	{0x12000b, 0x70},
-	{0x12000c, 0x19},
-	{0x12000d, 0xfa},
-	{0x12000e, 0x10},
-	{0x22000b, 0x1c},
-	{0x22000c, 0x6},
-	{0x22000d, 0x3e},
-	{0x22000e, 0x10},
 	{0x9000c, 0x0},
 	{0x9000d, 0x173},
 	{0x9000e, 0x60},
@@ -1713,28 +1642,12 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{0x90013, 0x6152},
 	{0x20010, 0x5a},
 	{0x20011, 0x3},
-	{0x120010, 0x5a},
-	{0x120011, 0x3},
-	{0x220010, 0x5a},
-	{0x220011, 0x3},
 	{0x40080, 0xe0},
 	{0x40081, 0x12},
 	{0x40082, 0xe0},
 	{0x40083, 0x12},
 	{0x40084, 0xe0},
 	{0x40085, 0x12},
-	{0x140080, 0xe0},
-	{0x140081, 0x12},
-	{0x140082, 0xe0},
-	{0x140083, 0x12},
-	{0x140084, 0xe0},
-	{0x140085, 0x12},
-	{0x240080, 0xe0},
-	{0x240081, 0x12},
-	{0x240082, 0xe0},
-	{0x240083, 0x12},
-	{0x240084, 0xe0},
-	{0x240085, 0x12},
 	{0x400fd, 0xf},
 	{0x10011, 0x1},
 	{0x10012, 0x1},
@@ -1794,7 +1707,7 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{0x138b4, 0x1},
 	{0x2003a, 0x2},
 	{0xc0080, 0x2},
-	{0xd0000, 0x1}
+	{0xd0000, 0x1},
 };
 
 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
@@ -1805,20 +1718,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 		.fsp_cfg = ddr_fsp0_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
 	},
-	{
-		/* P1 400mts 1D */
-		.drate = 400,
-		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = ddr_fsp1_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
-	},
-	{
-		/* P2 100mts 1D */
-		.drate = 100,
-		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = ddr_fsp2_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
-	},
 	{
 		/* P0 3000mts 2D */
 		.drate = 3000,
@@ -1840,5 +1739,55 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 3000, 400, 100,},
+	.fsp_table = { 3000, },
 };
+
+void set_dram_timings_1gb(void)
+{
+	dram_timing.ddrc_cfg[5].val = 0x2d0087;
+	dram_timing.ddrc_cfg[21].val = 0x8d;
+	dram_timing.ddrc_cfg[42].val = 0xf070707;
+}
+
+void set_dram_timings_4gb(void)
+{
+	dram_timing.ddrc_cfg[2].val = 0xa3080020;
+	dram_timing.ddrc_cfg[37].val = 0x17;
+	dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x310;
+	dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x3;
+	dram_timing.fsp_msg[1].fsp_cfg[11].val = 0x310;
+	dram_timing.fsp_msg[1].fsp_cfg[23].val = 0x3;
+}
+
+void set_dram_timings_rev7(void)
+{
+	dram_timing.ddrc_cfg[10].val = 0x55004d;
+	dram_timing.ddrphy_cfg[64].val = 0x618;
+	dram_timing.ddrphy_cfg[65].val = 0x618;
+	dram_timing.ddrphy_cfg[66].val = 0x618;
+	dram_timing.ddrphy_cfg[67].val = 0x618;
+	dram_timing.ddrphy_cfg[68].val = 0x618;
+	dram_timing.ddrphy_cfg[69].val = 0x618;
+	dram_timing.ddrphy_cfg[70].val = 0x618;
+	dram_timing.ddrphy_cfg[71].val = 0x618;
+	dram_timing.ddrphy_cfg[72].val = 0x63;
+	dram_timing.ddrphy_cfg[73].val = 0x63;
+	dram_timing.ddrphy_cfg[74].val = 0x63;
+	dram_timing.ddrphy_cfg[75].val = 0x63;
+	dram_timing.ddrphy_cfg[76].val = 0x63;
+	dram_timing.ddrphy_cfg[77].val = 0x63;
+	dram_timing.ddrphy_cfg[78].val = 0x63;
+	dram_timing.ddrphy_cfg[79].val = 0x63;
+	dram_timing.ddrphy_cfg[80].val = 0x63;
+	dram_timing.ddrphy_cfg[81].val = 0x63;
+	dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x3c30;
+	dram_timing.fsp_msg[0].fsp_cfg[11].val = 0x4d55;
+	dram_timing.fsp_msg[0].fsp_cfg[16].val = 0x4d55;
+	dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x5500;
+	dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x5500;
+	dram_timing.fsp_msg[1].fsp_cfg[3].val = 0x3c30;
+	dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x4d55;
+	dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x4d55;
+	dram_timing.fsp_msg[1].fsp_cfg[26].val = 0x5500;
+	dram_timing.fsp_msg[1].fsp_cfg[32].val = 0x5500;
+}
diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.h b/board/phytec/phycore_imx8mm/lpddr4_timing.h
new file mode 100644
index 00000000000..340fefe01c3
--- /dev/null
+++ b/board/phytec/phycore_imx8mm/lpddr4_timing.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void set_dram_timings_1gb(void);
+void set_dram_timings_4gb(void);
+void set_dram_timings_rev7(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
index 9f6a4ec704d..25e51dce739 100644
--- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c
+++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
@@ -9,6 +9,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <env.h>
 #include <miiphy.h>
+#include <init.h>
 
 static int setup_fec(void)
 {
@@ -50,3 +51,20 @@ int board_late_init(void)
 
 	return 0;
 }
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	/*
+	 * check various RAM sizes (1, 2 and 4 GB) otherwise
+	 * return the default of 2GB
+	 */
+	*size = get_ram_size((void *)PHYS_SDRAM,
+			     (long)PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+	if (*size == 0)
+		*size = SZ_2G;
+
+	return 0;
+}
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index e688793bc74..a3879881eb7 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -16,11 +16,19 @@
 #include <log.h>
 #include <spl.h>
 
+#include "lpddr4_timing.h"
 #include "../common/imx8m_som_detection.h"
 
 #define EEPROM_ADDR		0x51
 #define EEPROM_ADDR_FALLBACK	0x59
 
+enum phytec_imx8mm_ddr_eeprom_code {
+	INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX8MM_DDR_1GB = 1,
+	PHYTEC_IMX8MM_DDR_2GB = 3,
+	PHYTEC_IMX8MM_DDR_4GB = 5,
+};
+
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	switch (boot_dev_spl) {
@@ -42,17 +50,63 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 static void spl_dram_init(void)
 {
 	int ret;
+	enum phytec_imx8mm_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
+	u8 rev = PHYTEC_EEPROM_INVAL;
 
 	ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
 			EEPROM_ADDR_FALLBACK);
-	if (ret)
+	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX))
 		goto out;
 
 	ret = phytec_imx8m_detect(NULL);
 	if (!ret)
 		phytec_print_som_info(NULL);
 
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_1GB))
+			size = PHYTEC_IMX8MM_DDR_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_2GB))
+			size = PHYTEC_IMX8MM_DDR_2GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_4GB))
+			size = PHYTEC_IMX8MM_DDR_4GB;
+	} else {
+		size = phytec_get_imx8m_ddr_size(NULL);
+	}
+
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_STATIC_SOM_REV)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_6))
+			rev = 6;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_7))
+			rev = 7;
+	} else {
+		rev = phytec_get_rev(NULL);
+	}
+
+	if (rev >= 7 || rev == PHYTEC_EEPROM_INVAL) {
+		debug("%s: Using rev7 RAM timings.\n", __func__);
+		set_dram_timings_rev7();
+	} else {
+		debug("%s: Using rev6 RAM timings.\n", __func__);
+	}
+
+	switch (size) {
+	case PHYTEC_IMX8MM_DDR_1GB:
+		set_dram_timings_1gb();
+		break;
+	case PHYTEC_IMX8MM_DDR_2GB:
+		break;
+	case PHYTEC_IMX8MM_DDR_4GB:
+		set_dram_timings_4gb();
+		break;
+	default:
+		goto out;
+	}
+	ddr_init(&dram_timing);
+
+	return;
 out:
+	puts("Could not detect correct RAM size. Fall back to default.\n");
+	set_dram_timings_rev7();
 	ddr_init(&dram_timing);
 }
 
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 1998411ebde..0b1798dc812 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -201,6 +201,7 @@ const struct toradex_som toradex_modules[] = {
 	{ VERDIN_IMX8MMQ_2G_WIFI_BT_IT_64G,      "Verdin iMX8M Mini Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MM)        },
 	{ SMARC_IMX8MPQ_4GB_WB_IT_64G,           "SMARC iMX8M Plus Quad 4GB WB IT",      TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) },
 	{ VERDIN_AM62D_1G_WIFI_BT_ET,            "Verdin AM62 Dual 1GB WB ET",           TARGET_IS_ENABLED(VERDIN_AM62_A53)      },
+	{ AQUILA_IMX95_HEXA_8GB_IT,              "Aquila iMX95 Hexa 8GB IT",             TARGET_IS_ENABLED(AQUILA_IMX95)         },
 };
 
 struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index bf6a0861378..32305c61c83 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -164,6 +164,7 @@ enum {
 	VERDIN_IMX8MMQ_2G_WIFI_BT_IT_64G,
 	SMARC_IMX8MPQ_4GB_WB_IT_64G, /* 240 */
 	VERDIN_AM62D_1G_WIFI_BT_ET = 242,
+	AQUILA_IMX95_HEXA_8GB_IT,
 };
 
 enum {
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index 9dc7fe21820..3ae92ff09f6 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -4,6 +4,7 @@ CONFIG_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_PHYTEC_SOM_DETECTION=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x3C0000
 CONFIG_DM_GPIO=y
diff --git a/configs/imx95_15x15_frdm_defconfig b/configs/imx95_15x15_frdm_defconfig
new file mode 100644
index 00000000000..f2aa507ec3c
--- /dev/null
+++ b/configs/imx95_15x15_frdm_defconfig
@@ -0,0 +1,143 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x90200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SOURCE_FILE="imx95_frdm"
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/scmi/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx95-15x15-frdm"
+CONFIG_TARGET_IMX95_15X15_FRDM=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0x20480000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x204d6000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x90400000
+CONFIG_SPL=y
+CONFIG_SPL_RECOVER_DATA_SECTION=y
+CONFIG_PCI=y
+CONFIG_SYS_MEMTEST_START=0x90000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx95-15x15-frdm.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+# CONFIG_BOARD_INIT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_MMC_DEVICE_INDEX=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_RX_ETH_BUFFER=8
+CONFIG_SPL_DM=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_CLK_IMX95_BLKCTRL=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SPL_FIRMWARE=y
+# CONFIG_SCMI_AGENT_SMCCC is not set
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_ADP5585_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_IMX_MU_MBOX=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_MII=y
+CONFIG_FSL_ENETC=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX_SCMI=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_WDT=y
diff --git a/doc/board/nxp/imx95_frdm.rst b/doc/board/nxp/imx95_frdm.rst
new file mode 100644
index 00000000000..85ef9022e76
--- /dev/null
+++ b/doc/board/nxp/imx95_frdm.rst
@@ -0,0 +1,131 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx95_frdm
+=======================
+
+U-Boot for the NXP i.MX95 15x15 FRDM board
+
+Quick Start
+-----------
+
+- Get ahab-container.img
+- Get DDR PHY Firmware Images
+- Get and Build OEI Images
+- Get and Build System Manager Image
+- Get and Build the ARM Trusted Firmware
+- Build the Bootloader Image
+- Boot
+
+Get ahab-container.img
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin
+   $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept
+
+i.MX95 A0 silicon version
+
+.. code-block:: bash
+
+   $ cp firmware-ele-imx-2.0.2-89161a8/mx95a0-ahab-container.img $(srctree)
+
+i.MX95 B0 silicon version
+
+.. code-block:: bash
+
+   $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree)
+
+Get DDR PHY Firmware Images
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin
+   $ sh firmware-imx-8.28-994fa14.bin --auto-accept
+   $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree)
+   $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4x*v202409.bin $(srctree)
+
+Get and Build OEI Images
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get OEI from: https://github.com/nxp-imx/imx-oei
+branch: master
+
+.. code-block:: bash
+
+   $ sudo apt -y install make gcc g++-multilib srecord
+   $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+   $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+   $ export TOOLS=$PWD
+   $ git clone -b master https://github.com/nxp-imx/imx-oei.git
+   $ cd imx-oei
+
+i.MX95 B0 silicon version on 15x15 LPDDR4X FRDM Board
+
+.. code-block:: bash
+
+   $ make board=mx95lp4x-15 oei=ddr DEBUG=1 r=B0 all
+   $ cp build/mx95lp4x-15/ddr/oei-m33-ddr.bin $(srctree)
+
+Get and Build System Manager Image
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get System Manager from: https://github.com/nxp-imx/imx-sm
+branch: master
+
+.. code-block:: bash
+
+   $ sudo apt -y install make gcc g++-multilib srecord
+   $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+   $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz
+   $ export TOOLS=$PWD
+   $ git clone -b master https://github.com/nxp-imx/imx-sm.git
+   $ cd imx-sm
+   $ make config=mx95evk all
+   $ cp build/mx95evk/m33_image.bin $(srctree)
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.12
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ unset LDFLAGS
+   $ unset AS
+   $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git
+   $ cd imx-atf
+   $ make PLAT=imx95 bl31
+   $ cp build/imx95/release/bl31.bin $(srctree)
+
+Build the Bootloader Image
+--------------------------
+
+i.MX95 B0 silicon version on 15x15 LPDDR4X FRDM Board
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx95_15x15_frdm_defconfig
+   $ make
+
+Copy imx-boot-imx95.bin to the MicroSD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
+
+Boot
+----
+
+Set i.MX95 boot device to MicroSD card
diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst
index 52c8e85fa5b..b28e5b6ceb9 100644
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -17,6 +17,7 @@ NXP Semiconductors
    imx93_9x9_qsb
    imx93_11x11_evk
    imx93_frdm
+   imx95_frdm
    imx943_evk
    imx95_evk
    imx952_evk
diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
index 1bea091344d..a3ebd397d82 100644
--- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
@@ -167,17 +167,25 @@ The nxp-imx8mcst etype is configurable using either DT properties or environment
 variables. The following DT properties and environment variables are supported.
 Note that environment variables override DT properties.
 
-+--------------------+-----------+------------------------------------------------------------------+
-| DT property        | Variable  | Description                                                      |
-+====================+===========+==================================================================+
-| nxp,loader-address |           | SPL base address                                                 |
-+--------------------+-----------+------------------------------------------------------------------+
-| nxp,srk-table      | SRK_TABLE | full path to SRK_1_2_3_4_table.bin                               |
-+--------------------+-----------+------------------------------------------------------------------+
-| nxp,csf-crt        | CSF_KEY   | full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem |
-+--------------------+-----------+------------------------------------------------------------------+
-| nxp,img-crt        | IMG_KEY   | full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem |
-+--------------------+-----------+------------------------------------------------------------------+
++--------------------+-------------+------------------------------------------------------------------+
+| DT property        | Variable    | Description                                                      |
++====================+=============+==================================================================+
+| nxp,loader-address |             | SPL base address                                                 |
++--------------------+-------------+------------------------------------------------------------------+
+| nxp,srk-table      | SRK_TABLE   | full path to SRK_1_2_3_4_table.bin                               |
++--------------------+-------------+------------------------------------------------------------------+
+| nxp,csf-crt        | CSF_KEY     | full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem |
++--------------------+-------------+------------------------------------------------------------------+
+| nxp,img-crt        | IMG_KEY     | full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem |
++--------------------+-------------+------------------------------------------------------------------+
+| nxp,fast-auth      |             | enable fast authentication method                                |
++--------------------+-------------+------------------------------------------------------------------+
+| nxp,srk-crt        | SRK_KEY     | full path to the SRK Key SRK1_sha256_4096_65537_v3_ca_crt.pem    |
++--------------------+-------------+------------------------------------------------------------------+
+| nxp,unlock         |             | unlock CAAM in SPL                                               |
++--------------------+-------------+------------------------------------------------------------------+
+| nxp,cst-backend    | CST_BACKEND | CST tool backend, default is 'ssl', or selectable 'pkcs11'       |
++--------------------+-------------+------------------------------------------------------------------+
 
 Environment variables can be set as follows to point the build process
 to external key material:
diff --git a/include/configs/imx95_frdm.h b/include/configs/imx95_frdm.h
new file mode 100644
index 00000000000..132eea28643
--- /dev/null
+++ b/include/configs/imx95_frdm.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2026 NXP
+ */
+
+#ifndef __IMX95_EVK_H
+#define __IMX95_EVK_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_INIT_RAM_ADDR	0x90000000
+#define CFG_SYS_INIT_RAM_SIZE	0x200000
+
+#define CFG_SYS_SDRAM_BASE		0x90000000
+#define PHYS_SDRAM			0x90000000
+
+#define PHYS_SDRAM_SIZE			0x70000000 /* 2GB - 256MB DDR */
+
+#define PHYS_SDRAM_2_SIZE		0x180000000 /* 6GB (Totally 8GB) */
+
+#endif
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index 20e2ab832ee..d4571cc6f39 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -28,6 +28,7 @@
 #define CFG_SYS_SDRAM_BASE		0x40000000
 
 #define PHYS_SDRAM			0x40000000
-#define PHYS_SDRAM_SIZE                 SZ_2G /* 2GB DDR */
-
+#define PHYS_SDRAM_SIZE                 (SZ_2G + SZ_1G) /* 3GB */
+#define PHYS_SDRAM_2                    0x100000000
+#define PHYS_SDRAM_2_SIZE                SZ_1G /* 4GB DDR */
 #endif /* __PHYCORE_IMX8MM_H */
diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py
index dd9f226b751..29a7451678d 100644
--- a/tools/binman/etype/nxp_imx8mcst.py
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -20,8 +20,9 @@ from binman import elf
 from dtoc import fdt_util
 from u_boot_pylib import tools
 
-MAGIC_NXP_IMX_IVT = 0x412000d1
-MAGIC_FITIMAGE    = 0xedfe0dd0
+MAGIC_NXP_IMX_IVT  = 0x412000d1
+MAGIC_NXP_IMX_FCFB = 0x42464346
+MAGIC_FITIMAGE     = 0xedfe0dd0
 
 KEY_NAME = 'sha256_4096_65537_v3_usr_crt'
 
@@ -65,6 +66,13 @@ class Entry_nxp_imx8mcst(Entry_mkimage):
 
     Properties / Entry arguments:
         - nxp,loader-address - loader address (SPL text base)
+        - nxp,srk-table - full path to SRK_1_2_3_4_table.bin
+        - nxp,csf-crt - full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem
+        - nxp,img-crt - full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem
+        - nxp,fast-auth - enable fast authentication method
+        - nxp,srk-crt - full path to the SRK Key SRK1_sha256_4096_65537_v3_ca_crt.pem
+        - nxp,unlock - unlock CAAM in SPL
+        - nxp,cst-backend - CST tool backend, default is 'ssl', or selectable 'pkcs11'
     """
 
     def __init__(self, section, etype, node):
@@ -90,6 +98,10 @@ class Entry_nxp_imx8mcst(Entry_mkimage):
                 'SRK_KEY', fdt_util.GetString(self._node, 'nxp,srk-crt',
                                               f'SRK1_{KEY_NAME}.pem'))
 
+        self.backend = os.getenv(
+            'CST_BACKEND', fdt_util.GetString(self._node, 'nxp,cst-backend',
+                                              'ssl'))
+
         self.unlock = fdt_util.GetBool(self._node, 'nxp,unlock')
         self.ReadEntries()
 
@@ -101,6 +113,9 @@ class Entry_nxp_imx8mcst(Entry_mkimage):
         # - If it is mkimage'd imx8mimage, then extract to be signed data size
         #   from imx8mimage header, and calculate CSF blob offset right past
         #   the SPL from this information.
+        # - If it is mkimage'd imx8mimage wrapped in FCFB, then extract to be
+        #   signed data size from imx8mimage header past the FCFB header, and
+        #   calculate CSF blob offset right past the SPL from this information.
         # - If it is fitImage, then pad the image to 4k, add generated IVT and
         #   sign the whole payload, then append CSF blob at the end right past
         #   the IVT.
@@ -114,6 +129,17 @@ class Entry_nxp_imx8mcst(Entry_mkimage):
             signsize = struct.unpack('<I', data[24:28])[0] - signbase
             # Remove mkimage generated padding from the end of data
             data = data[:signsize]
+        elif signtype == MAGIC_NXP_IMX_FCFB: # SPL/imx8mimage with FCFB
+            # Sign the payload including FCFB and imx8mimage headers
+            # (extra 0x1000 and 0x40 bytes before the payload)
+            signbase -= 0x1040
+            # Pull the end address from IVT offset 24 Bytes and subtract
+            # the start address to get amount of data to sign. The IVT
+            # itself is at offset 4096 Bytes, so the total end address
+            # offset in the image is 4120 Bytes.
+            signsize = struct.unpack('<I', data[4120:4124])[0] - signbase
+            # Remove mkimage generated padding from the end of data
+            data = data[:signsize]
         elif signtype == MAGIC_FITIMAGE: # fitImage
             # Align fitImage to 4k
             signsize = tools.align(len(data), 0x1000)
@@ -161,8 +187,14 @@ class Entry_nxp_imx8mcst(Entry_mkimage):
         with open(cfg_fname, 'w') as cfgf:
             config.write(cfgf)
 
+        # SSL is the default backend, PKCS11 backend is optional
+        if self.backend == "pkcs11":
+            cst_backend = "pkcs11"
+        else:
+            cst_backend = "ssl"
+
         output_fname = tools.get_output_filename(f'nxp.csf-output-blob.{uniq}')
-        args = ['-i', cfg_fname, '-o', output_fname]
+        args = ['-i', cfg_fname, '-o', output_fname, '-b', cst_backend]
         if self.cst.run_cmd(*args) is not None:
             outdata = tools.read_file(output_fname)
             # fixme: 0x2000 should be CONFIG_CSF_SIZE
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 9553eb6b736..a0e8bde7901 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -8029,6 +8029,39 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         err = stderr.getvalue()
         self.assertRegex(err, "Image 'image'.*missing bintools.*: cst")
 
+    def testNxpImx8mCSTPKCS11(self):
+        """Test CST signing with IVT-format input (pkcs11 auth, no unlock)"""
+        # Create fake IVT blob: magic(4) + padding(20) + signsize_addr(4)
+        # + padding(36) = 64 bytes
+        ivt_data = struct.pack('<I', 0x412000d1)
+        ivt_data += b'\x00' * 20
+        ivt_data += struct.pack('<I', 0)
+        ivt_data += b'\x00' * 36
+        self._MakeInputFile('imx8m-ivt.bin', ivt_data)
+        with terminal.capture() as (_, stderr):
+            self._DoTestFile('vendor/nxp_imx8_csf_pkcs11.dts',
+                             force_missing_bintools='cst')
+        err = stderr.getvalue()
+        self.assertRegex(err, "Image 'image'.*missing bintools.*: cst")
+
+    def testNxpImx8mCSTFCFB(self):
+        """Test CST signing with FCFB-format input (normal auth, no unlock)"""
+        # Create fake FCFB blob: magic(4) + padding(4116)
+        ivt_data = struct.pack('<I', 0x42464346)
+        ivt_data += b'\x00' * 4116
+        # Create fake IVT blob: magic(4) + padding(20) + signsize_addr(4)
+        # + padding(36) = 64 bytes
+        ivt_data += struct.pack('<I', 0x412000d1)
+        ivt_data += b'\x00' * 20
+        ivt_data += struct.pack('<I', 0)
+        ivt_data += b'\x00' * 36
+        self._MakeInputFile('imx8m-ivt.bin', ivt_data)
+        with terminal.capture() as (_, stderr):
+            self._DoTestFile('vendor/nxp_imx8_csf.dts',
+                             force_missing_bintools='cst')
+        err = stderr.getvalue()
+        self.assertRegex(err, "Image 'image'.*missing bintools.*: cst")
+
     def testNxpImx8mCSTFastAuth(self):
         """Test CST signing with fast-auth mode, unlock, and FIT format"""
         # FIT magic covers the FIT-signing path; fast-auth/unlock cover the
diff --git a/tools/binman/test/vendor/nxp_imx8_csf_pkcs11.dts b/tools/binman/test/vendor/nxp_imx8_csf_pkcs11.dts
new file mode 100644
index 00000000000..835ea236826
--- /dev/null
+++ b/tools/binman/test/vendor/nxp_imx8_csf_pkcs11.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		nxp-imx8mcst {
+			args;
+			nxp,loader-address = <0x10>;
+			nxp,cst-backend = "pkcs11";
+
+			blob {
+				filename = "imx8m-ivt.bin";
+			};
+
+			imagename {
+				type = "section";
+
+				u-boot {
+				};
+			};
+		};
+	};
+};