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spi: cadence_qspi: Fix clearing of pol/pha bits

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Or'ing together bit positions is clearly wrong.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Phil Edworthy
2016-12-15 16:57:27 +01:00
committed by Jagan Teki
parent 1b7c28f514
commit cc80a897e4
1 changed files with 2 additions and 2 deletions
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drivers/spi/cadence_qspi_apb.c
+2 -2
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@@ -311,8 +311,8 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base,
cadence_qspi_apb_controller_disable(reg_base); cadence_qspi_apb_controller_disable(reg_base);
reg = readl(reg_base + CQSPI_REG_CONFIG); reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(1 << reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB);
(CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB);
reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);