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riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode

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The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.

Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Yu Chien Peter Lin
2023-10-04 18:23:54 +08:00
committed by Leo Yu-Chi Liang
parent 5f25297637
commit 8a0d5f2f51
3 changed files with 11 additions and 3 deletions
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drivers/timer/Kconfig
+8 -1
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@@ -59,7 +59,14 @@ config ALTERA_TIMER
config ANDES_PLMT_TIMER
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
depends on RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
config SPL_ANDES_PLMT_TIMER
bool
depends on SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.