From c125ef543c128a3351a564ce584e15e646cdb1df Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 9 Dec 2024 12:45:18 +0200 Subject: [PATCH 01/12] Revert "drivers: gpio-uclass: support PMIC GPIO children" Requesting of PMIC's GPIO child should be done by binding GPIO driver to PMIC's node is GPIO driver does not have its own node. This reverts commit c03cd98d1a163666b4addcdd9a34fc0c77dfd0a5. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Jaehoon Chung --- drivers/gpio/gpio-uclass.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index da929c33447..3d9f8b32b8d 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1145,29 +1145,9 @@ static int gpio_request_tail(int ret, const char *nodename, ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node, &desc->dev); if (ret) { -#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO) - struct udevice *pmic; - ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node, - &pmic); - if (ret) { - log_debug("%s: PMIC device get failed, err %d\n", - __func__, ret); - goto err; - } - - device_foreach_child(desc->dev, pmic) { - if (device_get_uclass_id(desc->dev) == UCLASS_GPIO) - break; - } - - /* if loop exits without GPIO device return error */ - if (device_get_uclass_id(desc->dev) != UCLASS_GPIO) - goto err; -#else debug("%s: uclass_get_device_by_ofnode failed\n", __func__); goto err; -#endif } } ret = gpio_find_and_xlate(desc, args); From 1ca8ec80f29a5a45dcb702a1164f9b42a077914f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 9 Dec 2024 12:51:33 +0200 Subject: [PATCH 02/12] pmic: max77663: bind children to parent node Bind GPIO and SYSRESET children to parent node since they do not have their own nodes in the device tree. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Jaehoon Chung --- drivers/power/pmic/max77663.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c index cf08b6a7e1d..c2a7cbf7e40 100644 --- a/drivers/power/pmic/max77663.c +++ b/drivers/power/pmic/max77663.c @@ -47,8 +47,9 @@ static int max77663_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) { - ret = device_bind_driver(dev, MAX77663_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; @@ -56,8 +57,8 @@ static int max77663_bind(struct udevice *dev) } if (IS_ENABLED(CONFIG_MAX77663_GPIO)) { - ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER, - "gpio", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_GPIO_DRIVER, + "gpio", dev_ofnode(dev), NULL); if (ret) { log_err("cannot bind GPIOs (ret = %d)\n", ret); return ret; From aab837d7fc776ef956d07f97ad15cb4256a146af Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 9 Dec 2024 12:58:19 +0200 Subject: [PATCH 03/12] pmic: palmas: bind sysreset to parent node Bind SYSRESET child to parent node since it does not have its own node in the device tree. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Jaehoon Chung --- drivers/power/pmic/palmas.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index f676bf64169..37d4190fabe 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -49,8 +49,9 @@ static int palmas_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { - ret = device_bind_driver(dev, PALMAS_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; From efb7964cc1613bed0550510116f11fe757c025f8 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 6 Dec 2024 17:50:58 +0200 Subject: [PATCH 04/12] pinctrl: tegra20: adjust pin type detection Pin detection on t20 depends on node name. With recent changes in node naming, let's remove '_' to be safe about both '_' or '-' use. Signed-off-by: Svyatoslav Ryhel --- drivers/pinctrl/tegra/pinctrl-tegra20.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index d5171b8be23..d59b3ec7b5d 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -97,9 +97,9 @@ static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config) * then actual pins setup (with node name prefix * conf_*) and then drive setup. */ - if (!strncmp(child->name, "conf_", 5)) + if (!strncmp(child->name, "conf", 4)) tegra_pinctrl_set_pin(child); - else if (!strncmp(child->name, "drive_", 6)) + else if (!strncmp(child->name, "drive", 5)) debug("%s: drive configuration is not supported\n", __func__); else tegra_pinctrl_set_func(child); From b93e25dc73acdc07c16074923aeeb305db21157a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 29 Nov 2024 19:30:54 +0200 Subject: [PATCH 05/12] board: asus: convert SPL to XPL Not sure why these files were omitted, but SPL should be converted to XPL. Signed-off-by: Svyatoslav Ryhel --- board/asus/grouper/Makefile | 2 +- board/asus/transformer-t30/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile index 8a8e6530c86..b83b7fced48 100644 --- a/board/asus/grouper/Makefile +++ b/board/asus/grouper/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel -obj-$(CONFIG_SPL_BUILD) += grouper-spl.o +obj-$(CONFIG_XPL_BUILD) += grouper-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += grouper.o diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile index 22b6160f757..b8617f820cd 100644 --- a/board/asus/transformer-t30/Makefile +++ b/board/asus/transformer-t30/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel -obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o +obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += transformer-t30.o From e4f5741c6dc3ba5d867336244c53eb092b273f60 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 15 Nov 2024 21:13:15 +0200 Subject: [PATCH 06/12] ARM: tegra124: clock: implement PLLD2 support PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra124/clock-tables.h | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index 9f531253153..055948ec07a 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* Special for Tegra124 */ /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL2, CLOCK_ID_CGENERAL3, CLOCK_ID_MEMORY2, diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 4ac0c10c597..0ea212f80e2 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -598,6 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -852,6 +854,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA124_CLK_PLL_D: case TEGRA124_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA124_CLK_PLL_D2: + case TEGRA124_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA124_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA124_CLK_PLL_E: @@ -1194,6 +1199,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; case CLOCK_ID_DP: return &clkrst->plldp; default: From c3d8c206dc62a79eda44b1492decfbace151d17e Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 29 Nov 2024 08:14:21 +0200 Subject: [PATCH 07/12] ARM: tegra210: clock: implement PLLD2 support PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra210/clock-tables.h | 2 +- arch/arm/mach-tegra/tegra210/clock.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index c6d7487e629..5c4d7fc84c4 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL_0, CLOCK_ID_CGENERAL_1, CLOCK_ID_CGENERAL2, diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 57ff0b2a19a..04708f97144 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -668,6 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -939,6 +941,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA210_CLK_PLL_D: case TEGRA210_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA210_CLK_PLL_D2: + case TEGRA210_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA210_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA210_CLK_PLL_E: @@ -1276,6 +1281,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; default: return NULL; } From f47a02825aa967cf1f62248d50c012a3821d7ebc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 24 Nov 2024 14:27:17 +0200 Subject: [PATCH 08/12] ARM: tegra30: dts: complete DSI nodes Sync DSI nodes with Linux tree. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra30.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 1177e2ab1f4..d5de1ecaf05 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -218,10 +218,29 @@ dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIB>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 84>; + reset-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; From dedc0468b2eec4d4b8918742eda7203fb1871178 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 18 Nov 2024 08:32:13 +0200 Subject: [PATCH 09/12] ARM: tegra124: dts: add missing DSI nodes Bind missing DSI and MIPI calibration devices. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra124.dtsi | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index ffec9cae09d..cac9b112302 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -136,6 +136,38 @@ status = "disabled"; }; + dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x54540000 0x00040000>; @@ -737,6 +769,13 @@ #thermal-sensor-cells = <1>; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0x70110000 0x100>, /* DFLL control */ From 279289e0cfb67265190ab85420264ad78bba099c Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 20 Nov 2024 09:26:38 +0200 Subject: [PATCH 10/12] ARM: tegra124: dts: mark HOST1X and DC with pre-relocation flag Same as on previous SoC generations this is required for proper video output work. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 +-------- arch/arm/dts/tegra124-u-boot.dtsi | 13 +++++++++++++ 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index 376dcdf68fb..8a629bfe703 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -4,16 +4,9 @@ * Written by Simon Glass */ -#include "tegra-u-boot.dtsi" +#include "tegra124-u-boot.dtsi" / { - host1x@50000000 { - bootph-all; - dc@54200000 { - bootph-all; - }; - }; - spi@7000d400 { spi-deactivate-delay = <500>; spi-max-frequency = <3000000>; diff --git a/arch/arm/dts/tegra124-u-boot.dtsi b/arch/arm/dts/tegra124-u-boot.dtsi index 7c119725528..6a02714a258 100644 --- a/arch/arm/dts/tegra124-u-boot.dtsi +++ b/arch/arm/dts/tegra124-u-boot.dtsi @@ -1,3 +1,16 @@ #include #include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + bootph-all; + dc@54200000 { + bootph-all; + }; + + dc@54240000 { + bootph-all; + }; + }; +}; From 9095fb12110e24cfb383f49f2d491686324c53a2 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 3 Dec 2024 12:50:45 +0200 Subject: [PATCH 11/12] doc: board: tegra: update device information Adjust and update existing manuals to reflect the most recent updates. Signed-off-by: Svyatoslav Ryhel --- doc/board/asus/grouper.rst | 12 ++++++------ doc/board/asus/transformer_t20.rst | 6 +++--- doc/board/asus/transformer_t30.rst | 13 +++++++------ doc/board/htc/endeavoru.rst | 9 ++++----- doc/board/lg/x3_t30.rst | 20 ++++++++++---------- doc/board/microsoft/surface-rt.rst | 4 ++-- doc/board/wexler/qc750.rst | 9 ++++----- 7 files changed, 36 insertions(+), 37 deletions(-) diff --git a/doc/board/asus/grouper.rst b/doc/board/asus/grouper.rst index d56a9ca3921..14469582907 100644 --- a/doc/board/asus/grouper.rst +++ b/doc/board/asus/grouper.rst @@ -25,7 +25,7 @@ along with cellular one. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make grouper_defconfig # For all grouper versions and tilapia $ make @@ -79,18 +79,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have cellular version, +use ``tilapia.bct``. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/asus/transformer_t20.rst b/doc/board/asus/transformer_t20.rst index d4bc12d1619..4f4f893c3a8 100644 --- a/doc/board/asus/transformer_t20.rst +++ b/doc/board/asus/transformer_t20.rst @@ -25,7 +25,7 @@ defconfig. Valid fragments are ``tf101.config``, ``tf101g.config`` and .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t20_defconfig tf101.config # For TF101 $ make @@ -84,8 +84,8 @@ encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ wheelie -1 --bl bootloader.bin --bct tf101.bct --odm 0x300d8011 || break + $ nvflash --resume --rawdevicewrite 0 2048 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst index bebc4b9fad3..012a38251aa 100644 --- a/doc/board/asus/transformer_t30.rst +++ b/doc/board/asus/transformer_t30.rst @@ -22,6 +22,7 @@ Build U-Boot U-Boot features ability to detect transformer device model on which it is loaded. The list of supported devices include: + - ASUS Transformer Prime TF201 - ASUS Transformer Pad (3G/LTE) TF300T/TG/TL - ASUS Transformer Infinity TF700T @@ -30,7 +31,7 @@ loaded. The list of supported devices include: .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t30_defconfig $ make @@ -84,18 +85,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/tf201.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that you should adjust bct file +name according to your device. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst index e0edefe28ae..53df2d09a6f 100644 --- a/doc/board/htc/endeavoru.rst +++ b/doc/board/htc/endeavoru.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make endeavoru_defconfig $ make @@ -72,16 +72,15 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst index 618b00d34e3..9ff75034b72 100644 --- a/doc/board/lg/x3_t30.rst +++ b/doc/board/lg/x3_t30.rst @@ -24,7 +24,7 @@ board defconfig. Valid fragments are ``p880.config`` and ``p895.config``. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make x3_t30_defconfig p895.config # For LG Optimus Vu $ make @@ -75,18 +75,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have Optimus 4x HD, +use ``p880.bct``. Flashing with a pre-loaded U-Boot ********************************* @@ -122,7 +122,7 @@ the user to use/partition it in any way the user desires. Self Upgrading -------------- -Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using -ability of u-boot to mount it). Enter bootmenu, choose update bootloader option -with Power button and U-Boot should update itself. Once the process is -completed, U-Boot will ask to press any button to reboot. +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC or MicroSD +card if it is supported (using ability of u-boot to mount it). Enter bootmenu, +choose update bootloader option with Power button and U-Boot should update itself. +Once the process is completed, U-Boot will ask to press any button to reboot. diff --git a/doc/board/microsoft/surface-rt.rst b/doc/board/microsoft/surface-rt.rst index b5645e79340..2b29cce40a9 100644 --- a/doc/board/microsoft/surface-rt.rst +++ b/doc/board/microsoft/surface-rt.rst @@ -14,7 +14,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make surface-rt_defconfig $ make @@ -38,4 +38,4 @@ directory with To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on eMMC. Additionally, if the Volume Down button is pressed while loading, the device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC -as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console. +as mass storage, fastboot, reboot, reboot RCM, poweroff and enter U-Boot console. diff --git a/doc/board/wexler/qc750.rst b/doc/board/wexler/qc750.rst index b61e40176b0..169629c7e47 100644 --- a/doc/board/wexler/qc750.rst +++ b/doc/board/wexler/qc750.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make qc750_defconfig $ make @@ -71,16 +71,15 @@ pre-loading just built U-Boot into RAM. Flashing with the NV3P protocol ******************************* -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +Nv3p is a custom Nvidia protocol used to recover bricked devices. Tegrarcm is +used to handle such state. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --bct qc750.bct --bl bootloader.bin + $ tegrarcm --bct qc750.bct --bootloader android_bootloader.bin --loadaddr 0x80108000 $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. From df48a95588f7dfb36c39e24a5c4777d2357d4f1d Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 28 Dec 2024 15:21:03 +0200 Subject: [PATCH 12/12] board: transformer-t30: fix model detection PCBID1 seems to be high not only on TF600T, but on TF700T as well, that caused boot failure for TF700T. Switching PCBID1 to PCBID7 should fix this issue. Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Signed-off-by: Svyatoslav Ryhel --- board/asus/transformer-t30/board-info.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/asus/transformer-t30/board-info.c b/board/asus/transformer-t30/board-info.c index a2b540c90b6..e72614164b4 100644 --- a/board/asus/transformer-t30/board-info.c +++ b/board/asus/transformer-t30/board-info.c @@ -11,14 +11,14 @@ #include /* - * PCB_ID[1] is kb_row5_pr5 * PCB_ID[3] is kb_col7_pq7 * PCB_ID[4] is kb_row2_pr2 * PCB_ID[5] is kb_col5_pq5 + * PCB_ID[7] is gmi_cs1_n_pj2 * * Project ID * ===================================================== - * PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project + * PCB_ID[7] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project * 0 0 0 0 TF201 * 0 0 0 1 P1801 * 0 0 1 0 TF300T @@ -45,10 +45,10 @@ static const char * const project_id_to_fdt[] = { [TF600T] = "tegra30-asus-tf600t", }; -static int id_gpio_get_value(u32 pingrp, u32 pin) +static int id_gpio_get_value(u32 pingrp, u32 func, u32 pin) { /* Configure pinmux */ - pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_func(pingrp, func); pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); pinmux_tristate_enable(pingrp); pinmux_set_io(pingrp, PMUX_PIN_INPUT); @@ -65,19 +65,19 @@ static int id_gpio_get_value(u32 pingrp, u32 pin) static int get_project_id(void) { - u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5; + u32 pcb_id3, pcb_id4, pcb_id5, pcb_id7; - pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5, - TEGRA_GPIO(R, 5)); pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7, - TEGRA_GPIO(Q, 7)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 7)); pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2, - TEGRA_GPIO(R, 2)); + PMUX_FUNC_KBC, TEGRA_GPIO(R, 2)); pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5, - TEGRA_GPIO(Q, 5)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 5)); + pcb_id7 = id_gpio_get_value(PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_FUNC_RSVD1, TEGRA_GPIO(J, 2)); /* Construct board ID */ - int proj_id = pcb_id1 << 3 | pcb_id5 << 2 | + int proj_id = pcb_id7 << 3 | pcb_id5 << 2 | pcb_id4 << 1 | pcb_id3; log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id,